Vertical Transistor Fabrication via Epitaxial Ion Distribution

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Solution Overview

Problem

Conventional vertical transistors face issues with uneven ion concentration distribution in the channel region, leading to leakage current and conduction failures due to limitations in ion-implant technology.

Innovation Solution

A method for fabricating vertical transistors using an epitaxial process to form uniform ion distribution in the first and second polarity layers, combined with the formation of integration layers and pillars, and the strategic placement of gates and insulation layers to ensure uniform ion distribution and prevent leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ion-implant method or diffusion method is used to form ion-implanted regions on pillars, then sources, channels and drains can be formed, but the ion concentration distribution becomes non-uniform (Gaussian distribution) leading to leakage current or conduction failure

Engineering Contradiction:
Improvetransistor qualityVSAvoidion concentration uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent changes the fundamental parameter of ion introduction from post-growth ion implantation/diffusion to in-situ doping during epitaxial growth. This allows precise control of ion concentration uniformity by controlling growth conditions rather than relying on ion-implant parameters, directly resolving the contradiction between reliability and manufacturing precision

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the mechanical ion-implant system with a chemical epitaxial growth system. Instead of physically implanting ions into pre-formed structures, the ions are incorporated during the chemical vapor deposition process, enabling uniform distribution through controlled chemical reactions rather than mechanical bombardment

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Ease of manufacture

If conventional ion-implant technology is used, then vertical transistor structure can be formed, but uneven ion concentration distribution occurs in the channel region

Engineering Contradiction:
Improvevertical transistor fabricationVSAvoidion concentration distribution
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent performs preliminary doping action during the epitaxial growth process itself, incorporating ions into the crystal structure as it forms. This preliminary incorporation ensures uniform distribution from the beginning, avoiding the need for subsequent ion-implant steps that would create non-uniform distributions

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses epitaxial growth as an intermediary process that mediates between the substrate and the final transistor structure. The controlled chemical environment of epitaxial growth acts as an intermediary mechanism to achieve uniform ion distribution that cannot be obtained through direct ion-implant methods

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method achieves high-quality vertical transistors with uniform ion distribution, reducing leakage current and enhancing transistor performance.

Implementation Method 1

Step S2: sequentially epitaxially growing a first polarity layer and a channel layer inside each first trench

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 2

ion-implanted regions are formed on the pillars via an ion-doping method or a diffusion method

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS8557646B2Method for fabricating a vertical transistor
Publication Date: 2013.10.15 REXCHIP ELECTRONICS
  • US8557646B2 patent drawing
  • US8557646B2 patent drawing
  • US8557646B2 patent drawing

AI summary

A method for fabricating a vertical transistor comprises steps: forming a plurality of first trenches in a substrate; sequentially epitaxially growing a first polarity layer and a channel layer inside the first trenches, and forming a first retard layer on the channel layer; etching the first retard layer and the channel layer along the direction vertical to the first trenches to form a plurality of pillars; respectively forming a gate on a first sidewall and a second sidewall of each pillar; removing the first retard layer on the pillar; and epitaxially growing a second polarity layer on the pillar. The present invention is characterized by using an epitaxial method to form the first polarity layer, the channel layer and the second polarity layer and has the advantage of uniform ion concentration distribution. Therefore, the present invention can fabricate a high-quality vertical transistor.