Vertical Transistor Fabrication for High-Density Memory Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for forming vertical transistors and conductive lines coupled therewith in memory cells face challenges in achieving efficient integration and high levels of integration, particularly in volatile memory cells like DRAM, where capacitors are used, and in capacitor-less zero-capacitor-one-transistor (0C1T) memory, such as ZRAM, which requires innovative fabrication techniques to enhance storage density and retention.
Innovation Solution
The method involves forming trenches in a semiconductor substrate, ion implanting conductivity modifying impurities, diffusing dopants, depositing conductive materials, and etching to create vertically oriented transistors and conductive lines that are electrically coupled, allowing for the formation of advanced memory cells with high integration levels, including capacitor-less configurations like ZRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional horizontal transistor orientation is used, then fabrication processes are well-established, but integration density and storage capacity are limited
Solution Approach 1:
The patent transitions from conventional horizontal transistor orientation to vertical orientation, utilizing the third dimension (depth) to increase integration density. The vertical transistor structure extends perpendicular to the substrate surface, allowing multiple transistors to be stacked in the vertical direction rather than only in the planar direction, thereby achieving higher storage capacity without increasing chip area.
Solution Approach 2:
The vertical transistor is divided into distinct functional segments including source region, channel region, gate regions (first and second gates positioned at different heights), and drain region. This segmentation allows independent optimization of each region and enables complex three-dimensional doping profiles through selective ion implantation at different stages of fabrication.
2Productivity
If vertical transistor structure is implemented, then integration density increases, but fabrication process complexity increases
Solution Approach 1:
The fabrication process employs preliminary actions by forming masking layers and performing ion implantation in a specific sequence before final structure completion. For example, first gate formation and associated doping are completed before second gate formation, allowing each step to be optimized independently. Sacrificial layers are deposited and patterned in advance to guide subsequent etching and doping operations.
Solution Approach 2:
Sacrificial intermediary layers are used to facilitate complex three-dimensional structure formation. These temporary layers are deposited, patterned, and etched to create the vertical transistor architecture, then removed after serving their guiding function. The intermediaries enable precise control over dopant placement and gate positioning without requiring direct manual intervention for each three-dimensional feature.
3Manufacturing precision
If ion implantation and diffusion processes are used, then dopant distribution precision improves, but manufacturing steps increase
Solution Approach 1:
The fabrication process employs periodic ion implantation and thermal diffusion cycles, where each cycle consists of dopant introduction followed by controlled thermal treatment. Multiple such periods are applied at different stages to build up the complex vertical doping profile, with each period contributing a specific dopant concentration gradient to the final structure.
Solution Approach 2:
The patent utilizes parameter changes in ion implantation by varying implant energy, dose, and angle across different processing stages. Energy levels are adjusted to achieve desired penetration depths, while dose variations create different dopant concentrations in source, channel, and drain regions. Thermal diffusion parameters (temperature, time, atmosphere) are also precisely controlled to achieve target dopant distributions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of high-density memory arrays with efficient electrical coupling, enhancing data storage capabilities and retention in both conventional DRAM and capacitor-less memory technologies like ZRAM, addressing the limitations of existing integration methods.
Implementation Method 1
ion implanting conductivity modifying impurities
Implementation Method 2
diffusing dopants
Data Source
AI summary
Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.