Vertical Transistor Fin Thickness Uniformity via Embedded Insulator
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Solution Overview
Problem
Existing vertical-type transistors face challenges in achieving uniform fin or channel thickness, which affects device performance, and current fabrication techniques are inefficient, leading to extraneous processing steps.
Innovation Solution
The method involves forming tapered fins with an embedded insulator layer or plug that serves as an etch stop, allowing for a straightened and uniform fin profile, and using thermal oxidation to create a uniform source/drain region with alternating topography, eliminating the need for an etch stop layer and reducing processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional fabrication techniques are used to form vertical transistors, then device footprint is reduced, but fin thickness uniformity deteriorates
Solution Approach 1:
An embedded insulator layer is formed at the bottom of the fin structure before the fin etching process. This preliminary action creates a stop layer that prevents over-etching and ensures uniform fin thickness across the substrate, directly resolving the contradiction between reduced device footprint and maintained fin thickness uniformity.
Solution Approach 2:
The embedded insulator layer acts as an intermediary element between the substrate and the fin structure. It serves as a physical barrier and etch stop that mediates the etching process, ensuring that fins are etched to a precise depth while maintaining uniform thickness, thus enabling both small device footprint and high manufacturing precision.
2Manufacturing precision
If etch stop layers are used to ensure uniform fin thickness, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The embedded insulator layer is formed by combining deposition and patterning steps with the existing fin formation process flow. By merging the etch stop layer formation into the standard fabrication sequence, the patent achieves uniform fin thickness without significantly increasing overall device complexity.
Solution Approach 2:
The embedded insulator layer automatically serves as both a structural element and an etch stop layer. The same layer that provides electrical isolation also prevents over-etching, eliminating the need for separate etch stop layers and reducing fabrication process complexity while maintaining manufacturing precision.
3Manufacturing precision
If additional processing steps are added to achieve uniform fins, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The embedded insulator layer is formed during the preliminary stages of fin fabrication, before the actual fin etching begins. This preliminary formation of the etch stop layer ensures that when etching occurs, uniform fin thickness is achieved without requiring additional corrective processing steps, thereby maintaining high productivity.
Solution Approach 2:
The embedded insulator layer enables continuous etching processing without interruptions or additional steps. The etch stop layer ensures that the etching process can proceed uniformly across the entire substrate in a single continuous operation, maintaining both manufacturing precision and high fabrication efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor performance by ensuring uniform channel thickness and reduces processing complexity, resulting in improved device performance and efficiency.
Implementation Method 1
forming tapered fins with an embedded insulator layer or plug that serves as an etch stop
Implementation Method 2
using thermal oxidation to create a uniform source/drain region with alternating topography
Data Source
AI summary
Method and structures for forming vertical transistors with uniform fin thickness. A structure includes: a substrate, a plurality of fins over the substrate, a top and a bottom source/drain region in contact with the plurality of fins, respectively, where the bottom source/drain region has an alternating topography, and a bottom spacer in contact with the bottom source/drain region, where the bottom spacer conforms to the alternating topography of the bottom-source drain region.