Vertical Transistor Gate Absence for High Packing Density
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Solution Overview
Problem
There is a need for improved methods and structures to achieve high packing density in CMOS vertical transistors, particularly for tight pitch fabrication, as existing technologies face challenges in efficiently packing CMOS vertical transistors with closely spaced p-type and n-type vertical FETs.
Innovation Solution
The proposed solution involves forming CMOS vertical transistors with a gate structure absent from the proximal sidewall of each semiconductor fin, allowing the fins to be spaced only by a dielectric material, thereby enabling a high packing density. This is achieved by forming a semiconductor structure with doped bottom and top portions, semiconductor fins, and dielectric fill portions between the fins, and subsequently forming gate structures along the sidewalls of the fins not covered by the dielectric fill.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate structures are formed on all sidewalls of semiconductor fins, then transistor control is improved, but device packing density decreases
Solution Approach 1:
The gate structure is selectively removed from the proximal sidewall of each semiconductor fin that faces the adjacent fin. This extraction of the gate structure from specific locations enables closer spacing of fins while maintaining adequate control on the remaining sidewalls, thereby resolving the contradiction between transistor control and device packing density
Solution Approach 2:
The gate structure is present on distal sidewalls of semiconductor fins but absent from proximal sidewalls. This local differentiation in gate structure placement provides tailored control where needed while maximizing spacing efficiency in regions where adjacent fins are in close proximity, thus balancing transistor control with high packing density
2Area of stationary object
If semiconductor fins are closely spaced to increase packing density, then device area is reduced, but fabrication complexity increases
Solution Approach 1:
The gate structure formation process is segmented into distinct regions: distal sidewalls receive gate structures while proximal sidewalls do not. This segmentation is achieved through selective masking and deposition techniques that treat different sidewall regions differently, enabling close fin spacing with manageable fabrication complexity
Solution Approach 2:
The gate structure is formed on sidewalls before the final fin spacing is established, allowing subsequent removal of gate material from proximal sidewalls. This preliminary formation followed by selective removal simplifies the overall fabrication process compared to attempting to form gates only on specific sidewalls from the outset
Data Source
AI summary
A complementary metal oxide semiconductor (CMOS) vertical transistor structure with closely spaced p-type and n-type vertical field effect transistors (FETs) is provided. After forming a dielectric material portion contacting a proximal sidewall of a first semiconductor fin for formation of a p-type vertical FET and a proximal sidewall of a second semiconductor fin for formation of an n-type vertical FET, a first gate structure is formed contacting a distal sidewall of the first semiconductor fin, and a second gate structure is formed contacting a distal sidewall of the second semiconductor fin. Because no gate structures are formed between the first and second semiconductor fins, the p-type vertical FET is spaced from the n-type FET only by the dielectric material portion.