Vertical Transistor Gate Alignment for Reduced Cell Height
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Solution Overview
Problem
Conventional vertical transistors face limitations in device density due to the need for sufficient space between metal gates for adequate electrical isolation, which restricts the reduction of cell height without compromising electrical performance.
Innovation Solution
The design features a metal gate substantially aligned with the vertical sidewall of the semiconductor channel region at the cell boundary, allowing for reduced end-to-end spacing between adjacent fins, thereby minimizing cell height while maintaining proper electrical isolation through strategic alignment and etching techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sufficient space is provided between metal gates for electrical isolation, then electrical isolation is maintained, but cell height cannot be reduced
Solution Approach 1:
The patent extracts the electrical isolation function from the metal gate structure itself and relocates it to a dedicated isolation structure (dielectric material) positioned between adjacent fins. This allows the metal gates to be aligned flush with fin sidewalls, reducing cell height while maintaining isolation through the extracted isolation structure rather than through gate spacing
Solution Approach 2:
The patent introduces a dielectric isolation structure as an intermediary element between adjacent fins and metal gates. This mediator provides the necessary electrical isolation without requiring increased spacing between metal gates, enabling reduced cell height while maintaining isolation performance
2Length of stationary object
If metal gate is aligned with vertical sidewall of channel region, then cell height is reduced, but electrical isolation becomes compromised
Solution Approach 1:
The patent applies preliminary action by pre-positioning the dielectric isolation structure between adjacent fins before forming or positioning the metal gates. This advance preparation ensures that when metal gates are aligned flush with fin sidewalls to minimize cell height, the isolation function is already in place and does not compromise electrical performance
Solution Approach 2:
The isolation function is extracted from the metal gate design and assigned to a separate dielectric structure, allowing the metal gate to be positioned as far inward as possible (flush with sidewalls) to minimize cell height while the extracted isolation structure maintains electrical separation
3Quantity of substance
If end-to-end spacing between fins is reduced, then fin density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs self-aligned fabrication techniques where the dielectric isolation structure and metal gate positions are determined by the fin geometry itself rather than requiring independent precise positioning. The fin sidewalls serve as self-aligned references for positioning isolation structures and gates, automatically ensuring proper spacing and alignment as fin density increases
Solution Approach 2:
The patent merges multiple functions into the fin structure itself - the fin serves as both the active channel element and the alignment reference for positioning isolation structures and gates. This integration eliminates the need for separate alignment processes, reducing manufacturing precision requirements even as fin density increases
Data Source
AI summary
A semiconductor structure including a vertical semiconductor channel region, a bottom source drain region arranged on a substrate below the vertical semiconductor channel region, and a metal gate disposed around the vertical semiconductor channel region, where a first end of the vertical semiconductor channel region is aligned with a first end of the metal gate.