Vertical Transistor Gate Dielectric Thickness Variation
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Solution Overview
Problem
The increasing demand for high-capacity semiconductor devices with reduced size poses challenges in achieving efficient integration, particularly in maintaining uniformity and reliability of gate dielectric layers and channel structures in vertical transistor structures.
Innovation Solution
The semiconductor device features vertically stacked gate electrodes with channel holes extending perpendicularly to the substrate, incorporating a gate dielectric layer with varying thicknesses and shapes, and a channel area surrounded by a dielectric layer with distinct outer and inner circumferences, optimized through specific etching and deposition processes to minimize thickness and shape variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical transistor structures are used to increase integration density, then device capacity and integration degree are improved, but maintaining uniformity and reliability of gate dielectric layers becomes more difficult
Solution Approach 1:
The gate dielectric layer is designed with varying thicknesses at different locations - thicker at the bottom portion and thinner at the top portion. This local quality variation allows the structure to accommodate the vertical stacking requirements while maintaining reliable electrical characteristics at each level, resolving the contradiction between high integration density and manufacturing precision.
2Reliability
If gate dielectric layer thickness is varied at different locations, then reliability and operational characteristics are improved, but manufacturing complexity increases
Solution Approach 1:
The gate dielectric layer structure is designed in advance with predetermined varying thicknesses before the vertical stacking process. By preparing the dielectric layer with the optimal thickness profile beforehand, the subsequent stacking and formation processes become more straightforward, reducing overall manufacturing complexity while ensuring device reliability.
3Ease of operation
If channel holes are formed with different shapes and circumferences, then operational characteristics such as programming voltages and speeds are improved, but etching process difficulty increases
Solution Approach 1:
The channel holes are designed with controlled variations in shape and circumference parameters - including different outer and inner circumferences and convexities relative to the vertical axis. These parameter changes are optimized to achieve desired programming voltages and speeds while remaining within the capabilities of standard etching processes, balancing performance improvement with manufacturing ease.
Data Source
AI summary
A semiconductor device includes gate electrodes vertically stacked on a substrate, and channel holes passing through the gate electrodes to extend perpendicularly to the substrate and including a gate dielectric layer and a channel area. The gate dielectric layer may be formed of a plurality of layers, and at least one layer among the plurality of layers may have different thicknesses in different locations.