Vertical Transistor Gate Electrode Charge Leakage Mitigation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices are miniaturized, the reduction in cell capacitance leads to a decrease in retention time due to increased leakage of charges, which affects the performance and reliability of the device.
Innovation Solution
The semiconductor device incorporates a vertical transistor structure with a second gate electrode and storage node contact plugs having an n-p-n structure, which accumulates leaked charges using floating body characteristics, thereby minimizing charge loss and maintaining retention time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are reduced in size, then device integration density is improved, but cell capacitance is reduced leading to decreased retention time
Solution Approach 1:
A second gate electrode is introduced as an intermediary structure between the storage node and the substrate. This second gate electrode captures leaked charges that would otherwise be lost to the substrate, acting as a mediator to prevent charge loss and maintain retention time even as cell capacitance decreases due to device miniaturization.
Solution Approach 2:
The second gate electrode is positioned and configured to preemptively capture leakage currents before they can cause significant charge loss. By having this charge capture mechanism in place beforehand, the system counteracts the natural tendency toward charge leakage that becomes more pronounced as devices are scaled down.
2Volume of moving object
If cell capacitance is reduced, then device size is reduced, but charge storage capability is reduced leading to increased charge leakage
Solution Approach 1:
The invention transitions from a planar charge storage architecture to a three-dimensional structure by adding the second gate electrode that wraps around or positions itself relative to the storage node contact plug. This vertical dimension provides additional surface area for charge capture without increasing the lateral footprint of the device, thereby maintaining small device size while improving charge storage reliability.
Solution Approach 2:
The second gate electrode is nested around or positioned in close proximity to the storage node contact plug, creating a nested configuration where the smaller gate structure is integrated within or adjacent to the larger storage node structure. This nested arrangement maximizes the charge capture surface area within the constrained volume of the miniaturized device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents charge leakage from the cell capacitor, maintaining retention time and improving the overall performance of the semiconductor device even with reduced cell capacitance.
Implementation Method 1
a vertical transistor includes the second gate electrode and the corresponding storage node contact plug and stores charges leaked from a corresponding one of the storage nodes
Data Source
AI summary
A semiconductor device includes a plurality of first gate electrodes buried in a semiconductor substrate including an active region and a device isolation film, a plurality of junction regions including storage node junction regions and a bit line junction region disposed between the storage node junction regions, a plurality of storage node contact plugs respectively disposed over and coupled to the storage node junction regions, a plurality of storage nodes respectively disposed over and coupled to the storage node contact plugs, and a second gate electrode disposed over a sidewall of a corresponding one of the storage node contact plugs. A vertical transistor includes the second gate electrode and the corresponding storage node contact plug and stores charges leaked from a corresponding one of the storage nodes.