Vertical Transistor Gate Formation via Selective Etch Back

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Solution Overview

Problem

Conventional semiconductor manufacturing processes result in uneven bottom surfaces of ditches, leading to excessive etching of metal wires, potential damage, and increased risk of current leakage due to lateral etching and uneven etching rates.

Innovation Solution

A method involving forming a substrate with opposing support portions to create a ditch, applying a conductive layer via chemical vapor deposition, using an etch back process for selective removal, forming an oxidized portion, and etching to create independent gates without contact, thereby addressing the issues of lateral etching and uneven surfaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional etching processes are used to form ditches, then the substrate can be etched to create trenches, but the bottom surface becomes uneven due to lateral etching and different etching rates

Engineering Contradiction:
Improvebottom surface uniformityVSAvoidetching process complexity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by forming a protective layer on the substrate surface before the etching process. This protective layer prevents lateral etching and ensures that the etching proceeds only vertically, resulting in a uniform bottom surface without the need for complex multi-stage etching processes.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If excessive etching is performed to fully separate the metal wire, then the metal wire becomes thinner and more prone to damage, but incomplete etching leaves non-separated sections that cause short circuits

Engineering Contradiction:
Improvemetal wire separation completenessVSAvoidmetal wire thickness
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The patent uses preliminary action by pre-forming a protective layer that extends into the ditch and covers the bottom surface. This protective layer acts as a stop etch layer during the etching process, allowing precise control of etching depth and preventing over-etching that would thin and damage the metal wire, while ensuring complete separation where needed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies local quality by making the protective layer have different properties in different locations - it provides etching protection on the bottom surface while allowing metal wire separation in specific regions. This localized differentiation enables precise control over where separation occurs without compromising metal wire strength elsewhere.

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If the bottom surface is uneven, then the bonding surface between metal wire and substrate becomes uneven, but flattening the surface requires additional processing steps

Engineering Contradiction:
Improvebonding surface uniformityVSAvoidfabrication process steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming the protective layer before etching, which prevents the formation of an uneven bottom surface in the first place. This proactive approach eliminates the need for subsequent flattening or planarization steps, reducing overall fabrication complexity while ensuring bonding surface uniformity.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures a smooth conductive layer formation coinciding with the substrate shape, reduces material waste, prevents short circuits, and enhances the reliability of metal wire separation and layer stacking, thereby improving production yield and reducing the risk of damage and current leakage.

Implementation Method 1

Covering a conductive layer on the bottom wall and side walls of the ditch and the top walls of the support portions via chemical vapor deposition

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Data Source

PatentUS8613861B2Method of manufacturing vertical transistors
Publication Date: 2013.12.24 MICRON TECHNOLOGY INC
  • US8613861B2 patent drawing
  • US8613861B2 patent drawing
  • US8613861B2 patent drawing

AI summary

A method of manufacturing vertical transistors includes steps of: forming a conductive layer on the surface of a substrate with a ditch and two support portions; removing the conductive layer on the bottom wall of the ditch and top walls of the support portions via anisotropic etching through a etch back process; forming an oxidized portion in the ditch; and etching the conductive layer to form two gates without contacting each other. By forming the conductive layer on the surface of the ditch and adopting selective etching of the etch back process, the problem of forming sub-trenches caused by lateral etching or uneven etching rate that might otherwise occur in the conventional etching process is prevented, and the risk of damaging metal wires caused by increasing etching duration also can be averted.