Vertical Transistor Gate Formation Using Self-Aligned Recess Etching
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Solution Overview
Problem
The complexity and cost-intensive process of forming transistors with a floating body effect in capacitorless memory devices require reduction in the number of photomasks used, as conventional methods involve multiple photomasks, increasing time and expense.
Innovation Solution
A method for forming vertical transistors with a floating body effect that reduces the number of photomasks by depositing gate conductor material within recesses of a semiconductor substrate and etching it to form front and back gates, eliminating the need for a conventional photomask, and using self-aligned contact techniques to form isolation and source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional photomask methods are used to form transistors with floating body effect, then manufacturing precision can be maintained, but device complexity and manufacturing cost increase due to requiring six or more photomasks
Solution Approach 1:
The gate conductor material deposition and etching process serves itself to define the gate patterns without requiring external photomasks. The self-aligned contact techniques similarly use the deposited materials themselves as alignment references, eliminating the need for separate photomask alignment steps and reducing overall process complexity
Solution Approach 2:
The patent extracts and removes the photomask step from the conventional transistor fabrication process. By using direct deposition and etching of gate conductor material to define gate patterns, the method eliminates the need for photomasks entirely in the gate formation process, reducing the total number of photomasks from six or more to just three
2Manufacturing precision
If multiple photomasks are used in the transistor formation process, then precise pattern definition can be achieved, but manufacturing time and cost increase
Solution Approach 1:
The patent merges multiple separate photomask steps into a single integrated deposition and etching process. The gate conductor material is deposited in one step and patterned in another, combining functions that previously required separate photomask applications. Self-aligned contact techniques further merge alignment and contact formation into unified process steps, reducing total manufacturing cycle time while maintaining precision
Solution Approach 2:
The gate conductor material is deposited in advance as a continuous layer that will be subsequently patterned. This preliminary deposition action allows the material to be in place before patterning, enabling self-aligned contact formation and eliminating the need for multiple sequential photomask steps, thereby reducing manufacturing time while preserving pattern definition accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces costs, and allows for the formation of transistors with a floating body effect using only three photomasks, enhancing data access speed and reducing power consumption while maintaining device scalability.
Implementation Method 1
depositing gate conductor material within recesses of a semiconductor substrate
Implementation Method 2
depositing gate conductor material within recesses of a semiconductor substrate
Implementation Method 3
etching it to form front and back gates
Data Source
AI summary
A vertical transistor forming method includes forming a first pillar above a first source/drain and between second and third pillars, providing a first recess between the first and second pillars and a wider second recess between the first and third pillars, forming a gate insulator over the first pillar, forming a front gate and back gate over opposing sidewalls of the first pillar by depositing a gate conductor material within the first and second recesses and etching the gate conductor material to substantially fill the first recess, forming the back gate, and only partially fill the second recess, forming the front gate, forming a second source/drain elevationally above the first source/drain, and providing a transistor channel in the first pillar. The channel is operationally associated with the first and second sources/drains and with the front and back gates to form a vertical transistor configured to exhibit a floating body effect.