Vertical Transistor Gate Layer Etch Mask Integration
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Solution Overview
Problem
The manufacturing of vertical transistor devices in semiconductor fabrication is complex and expensive, requiring improved methods for forming pillars that can be used to create these devices effectively.
Innovation Solution
A method involving a stack of layers where the gate layer acts as both an etch mask and a gate electrode, allowing for self-alignment and reducing the number of processing steps by patterning the fin into pillars, with selective dielectric deposition to isolate source and drain regions from the gate layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a separate etch mask layer is used for patterning fins into pillars, then the patterning precision is improved, but the device complexity and number of processing steps increase
Solution Approach 1:
The patent combines the etch mask function and gate electrode function into a single gate layer structure. This gate layer is deposited conformally on the fin structure and then anisotropically etched to create self-aligned patterns that serve both as etch masks for defining pillars and as the final gate electrodes, eliminating the need for separate etch mask deposition and removal steps.
Solution Approach 2:
The gate layer is designed to perform multiple functions simultaneously: it acts as the gate electrode for electrical control, as an etch mask for defining the pillar geometry through anisotropic etching, and as a template for self-aligned patterning. This multi-functionality reduces the overall number of processing steps while maintaining manufacturing precision.
2Manufacturing precision
If multiple separate layers are used for etch mask and gate electrode, then the manufacturing precision is improved, but the ease of manufacture deteriorates
Solution Approach 1:
The gate layer structure performs self-alignment through conformal deposition on the fin sidewalls followed by anisotropic etching. The etching process automatically aligns the gate pattern with the fin structure, eliminating the need for separate alignment steps and photolithography processes that would be required if separate etch mask and gate electrode layers were used.
Solution Approach 2:
By merging the etch mask and gate electrode into a single conformally deposited layer, the patent achieves both high alignment precision through self-alignment and improved ease of manufacture by reducing the number of deposition, patterning, and etching steps required in conventional separate-layer approaches.
3Reliability
If conventional separate etch mask and gate electrode processes are used, then the device functionality is ensured, but the productivity decreases due to increased processing steps
Solution Approach 1:
The conformal deposition of the gate layer continuously covers the fin sidewalls, and the subsequent anisotropic etching continuously removes material to define the pillar structure while simultaneously forming the gate electrode pattern. This continuous process eliminates idle steps between etch mask formation and gate electrode creation, improving productivity while ensuring device functionality.
Solution Approach 2:
The patent merges multiple discrete processing steps (etch mask deposition, etch mask patterning, pillar etching, gate electrode deposition) into a more integrated sequence where a single conformal layer serves multiple purposes, thereby reducing total processing time and improving productivity without compromising device functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the processing of vertical transistor devices, reduces the number of processing steps, and enables efficient formation of dense device integrations, such as CMOS and SRAM devices, by utilizing a single gate layer for both etching and electrode functions.
Implementation Method 1
providing a gate layer forming an etch mask arranged above the third layer; and etching at least the second and third layer through the etch mask to form a pillar of the fin
Implementation Method 2
The gate layer may thus be provided in the form of, e.g., an electrically conductive material that is deposited on the vertical sidewalls of the fins (to form the gate electrode)
Data Source
AI summary
The disclosed technology generally relates to semiconductor fabrication and more particularly to forming vertical transistor devices. In an aspect, a method of forming a vertical transistor device includes forming, on a substrate, a fin comprising a stack including a first layer, a second layer formed above the first layer and a third layer formed above the second layer. The method additionally includes forming a gate layer serving as an etch mask above the third layer. The method further includes etching the second and third layers of the fin using the gate layer as the etch mask to form a pillar. First and third layers of the pillar define a source region and a drain region, respectively, of the vertical transistor device. A second layer of the pillar defines a channel region of the vertical transistor device. The gate layer comprises a gate electrode arranged on at least one sidewall of the second layer.