Vertical Transistor Gate Contact Layout for Higher Density
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Solution Overview
Problem
Device density and resistance issues in vertical transistors limit their scalability and integration, particularly due to tall gate contacts and overlay problems leading to short circuits.
Innovation Solution
A vertical transistor structure with a reduced cell height is achieved by positioning a raised gate contact above the fin region, allowing for closer end-to-end spacing between adjacent fins and reducing resistance through a raised gate structure and gate contact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate contact is positioned at the bottom of the fin region, then manufacturing is simpler, but cell height increases and device density decreases
Solution Approach 1:
The gate contact is repositioned from the lateral bottom position to a vertical position above the fin region, utilizing the third dimension (vertical space) to resolve the contradiction. This allows the gate contact to be formed at a higher elevation where it can overlap with the fin region in the lateral projection, thereby reducing cell height while maintaining manufacturing feasibility through standard deposition and etching processes.
2Ease of manufacture
If gate contact extends below the fin region, then manufacturing is easier, but resistance increases due to longer contact path
Solution Approach 1:
The gate contact is elevated to extend above the fin region rather than below it, shortening the vertical path length through the contact region. This dimensional repositioning reduces the resistance by minimizing the conduction path length while still allowing the contact to be formed using standard bottom-up deposition techniques, as the contact material is deposited conformally and then planarized.
3Manufacturing precision
If fins are spaced further apart, then manufacturing precision is easier to achieve, but device density decreases
Solution Approach 1:
The gate contact is positioned in the vertical dimension above the fin region, allowing lateral projection overlap between the gate contact and fin region. This enables fins to be spaced closer together in the lateral plane without compromising manufacturing precision, as the gate contact formation process can accommodate tighter spacing when viewed from the lateral perspective while maintaining adequate vertical clearance.
4Quantity of substance
If cell height is reduced, then device density increases, but overlay problems may cause short circuits
Solution Approach 1:
The gate contact is repositioned to extend above the fin region in the vertical dimension, creating spatial separation between the gate contact and the fin region in the vertical direction. This allows the gate contact to overlap with the fin region in lateral projection without causing short circuits, as the vertical elevation difference prevents electrical contact. This resolves the overlay problem while enabling reduced cell height and increased device density.
Data Source
AI summary
A semiconductor structure including a vertical semiconductor channel region, a bottom source drain region arranged on a substrate at a bottom of the vertical semiconductor channel region, a metal gate disposed around the vertical semiconductor channel region, where a first portion of the metal gate extends above the vertical semiconductor channel region, and a gate contact entirely above the vertical semiconductor channel region.