Vertical Transistors with Variable Gate Lengths
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Solution Overview
Problem
Modern integrated circuits require transistors with different characteristics, such as switching speed and power consumption, to enhance performance and efficiency, but existing methods struggle to effectively form vertical transistor devices with varying gate lengths.
Innovation Solution
The method involves forming vertical transistor devices with different gate structures and spacer thicknesses, including doped source/drain regions and spacers, using techniques like etching, ion implantation, and deposition processes to achieve varying effective gate lengths, allowing for the creation of both NMOS and PMOS devices with specific performance characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If vertical transistor devices with different gate lengths are required to improve circuit performance and power consumption, then device characteristics and efficiency are enhanced, but existing manufacturing methods struggle to effectively form such devices with varying gate lengths
Solution Approach 1:
The patent divides the gate structure formation into separate stages: first forming a common gate structure across all transistor regions, then selectively removing gate material in specific regions to create different effective gate lengths. This segmentation allows different gate length configurations to be manufactured using the same base process sequence, improving adaptability without significantly increasing manufacturing complexity
Solution Approach 2:
The patent applies local quality by selectively modifying the gate structure in specific regions while maintaining uniform gate structures in other regions. Through selective etching or removal of gate material in designated areas, transistors with different effective gate lengths are created from a common gate structure, enabling diverse device characteristics while using standardized manufacturing processes
2Productivity
If transistors with different characteristics are used to enhance performance and power consumption, then circuit efficiency is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary action by forming a complete gate structure across all transistor regions before any selective modification. This initial uniform gate structure is then selectively altered in specific regions to create different effective gate lengths. The preliminary formation of the common gate structure simplifies subsequent processing steps and enables efficient manufacturing of diverse transistor characteristics
Solution Approach 2:
Instead of forming different gate structures from scratch for each transistor type, the patent inverts the approach by starting with a uniform gate structure and selectively removing or modifying it to create variations. This reverse engineering approach reduces manufacturing complexity while achieving the desired diversity in transistor characteristics for improved circuit efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the manufacturing of vertical transistor devices with tailored gate lengths, improving switching speed and power consumption, thereby enhancing the performance and efficiency of integrated circuits.
Implementation Method 1
using techniques like etching, ion implantation, and deposition processes
Implementation Method 2
using techniques like etching, ion implantation, and deposition processes
Data Source
AI summary
A device includes, among other things, a first vertical transistor device positioned above a semiconductor substrate. The first vertical transistor device includes a first gate structure, a first top spacer positioned above the first gate structure and having a first thickness in a vertical direction, and a first doped top source/drain structure positioned above the first top spacer. A second vertical transistor device positioned above the semiconductor substrate includes a second gate structure, a second top spacer positioned above the second gate structure and having a second thickness in a vertical direction less than the first thickness, and a second doped top source/drain structure positioned above the second top spacer.