Vertical Transistor Gate Offset via Sacrificial Oxide Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods face challenges in forming transistor gates within tight spaces between vertical semiconductor material pillars, limiting the packing density of vertical transistors in integrated circuit fabrication.
Innovation Solution
The method involves forming oxide layers within the spaces between pillars to offset the transistor gates, allowing for the use of sacrificial materials and etching techniques to narrow these spaces, enabling the fabrication of vertical transistors with tight aspect ratios, such as 8:1 to 10:1 or greater.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertical transistors are tightly packed to increase integration density, then the footprint area is reduced, but the fabrication difficulty of forming gates within tight spaces increases
Solution Approach 1:
The patent applies preliminary action by forming oxide layers at the bottoms of spaces between pillars before forming the transistor gates. This preliminary oxide formation enables subsequent gate formation in tight spaces by providing a foundation that facilitates the gate fabrication process, allowing gates to be successfully formed in tightly packed vertical transistor configurations
Solution Approach 2:
The patent uses oxide layers as an intermediary material formed at the bottoms of spaces between pillars. This intermediary oxide layer mediates the fabrication process by enabling gate formation in tight spaces, serving as a bridge between the pillar structure and the gate that needs to be formed within the constrained space
2Quantity of substance
If the spaces between pillars are narrowed to increase packing density, then the integration level increases, but the aspect ratio of spaces becomes more challenging to fabricate
Solution Approach 1:
The patent forms oxide layers preliminarily at the bottoms of spaces between pillars before attempting to form gates. This preliminary action enables the fabrication of gates in spaces with challenging aspect ratios (8:1 to 10:1 or greater) by providing a prepared foundation that makes the subsequent gate formation process feasible
Solution Approach 2:
The patent changes the physical and chemical parameters of the space between pillars by forming oxide layers within these spaces. This parameter change (adding oxide material) transforms the space characteristics, enabling gate formation in tightly packed configurations with aspect ratios of 8:1 to 10:1 or greater that would otherwise be difficult to fabricate
Data Source
AI summary
Some embodiments include methods of forming vertical transistors. A construction may have a plurality of spaced apart fins extending upwardly from a semiconductor substrate. Each of the fins may have vertical transistor pillars, and each of the vertical transistor pillars may have a bottom source/drain region location, a channel region location over the bottom source/drain region location, and a top source/drain region location over the channel region location. Electrically conductive gate material may be formed along the fins while using oxide within spaces along the bottoms of the fins to offset the electrically conductive gate material to be above the bottom source/drain region locations of the vertical transistor pillars. The oxide may be an oxide which etches at a rate of at least about 100 Å/minute with dilute HF at room temperature. In some embodiments the oxide may be removed after the electrically conductive gate material is formed.