3D Vertical Transistor Gate Segmentation for Interference Reduction
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Solution Overview
Problem
Transistors arranged in 2D or 3D configurations experience property degradation due to interference between adjacent devices, leading to suboptimal performance in electronic devices.
Innovation Solution
A transistor design featuring a pillar with a gate electrode comprising a first conductive pattern surrounding the pillar and multiple second conductive patterns protruding from it, spaced apart, along with an insulating pattern between the pillar and the first conductive pattern, and a sub-gate connecting stacked main gates, which improves the uniformity of the electric field and reduces interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are arranged in 2D or 3D configurations to increase data storage capacity and performance, then the data storage capacity and device diversity are improved, but the transistor properties are degraded due to interference between adjacent transistors
Solution Approach 1:
The patent transitions from conventional 2D transistor arrangement to a 3D vertical transistor structure where the channel extends in the vertical direction through stacked gate electrodes. This dimensional change allows increased storage capacity without the interference problems that plague planar arrangements, as each vertical transistor occupies its own spatial column with proper isolation.
Solution Approach 2:
The transistor structure is segmented into multiple components: the channel layer is divided into first and second regions separated by an insulating layer, and the gate electrode is divided into multiple stacked gate electrodes. This segmentation creates electrical isolation between adjacent transistor regions while maintaining the vertical structure, thereby preventing interference between horizontally adjacent transistors.
2Productivity
If transistors are stacked in 3D to improve properties, then the data storage capacity increases, but the transistor properties are degraded by interference between adjacent transistors in the stacking direction
Solution Approach 1:
The channel layer is segmented into first and second regions separated by an insulating layer positioned between the stacked gate electrodes. This segmentation creates electrical isolation in the vertical stacking direction, preventing interference between adjacent transistors while allowing multiple gates to control different portions of the channel independently.
Solution Approach 2:
An insulating layer is introduced as an intermediary between the first and second channel regions, and between the stacked gate electrodes. This intermediary layer provides electrical isolation that prevents interference between vertically stacked transistor components while maintaining the 3D structure necessary for high storage capacity.
3Reliability
If a conventional gate structure is used, then the device complexity is low, but the electric field uniformity and swing property are insufficient
Solution Approach 1:
The gate electrode is segmented into multiple stacked gate electrodes that can be independently controlled. This segmentation allows different voltage potentials to be applied to different gate regions, creating a more uniform electric field distribution across the channel and improving the swing property of the transistor.
Solution Approach 2:
The gate structure transitions from a single planar gate to multiple stacked gates extending in the vertical dimension. This dimensional change allows the electric field to be distributed more uniformly through the channel volume, improving control over the channel and enhancing swing properties while accepting increased structural complexity.
Data Source
AI summary
Provided is a semiconductor device including a pillar, a gate electrode having a first conductive pattern surrounding the pillar and a plurality of second conductive patterns which protrude from the first conductive pattern and are arranged to be spaced apart from each other, and an insulating pattern interposed between the pillar and the first conductive pattern.