Vertical Transistor Gate Formation via Segmented Hard Masks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for manufacturing semiconductor devices with vertical transistors face issues such as nitride hard masks and silicon pillars leaning, etch loss of the semiconductor substrate, and short circuits between adjoining gates due to thick nitride layers and polysilicon residue on sidewalls.
Innovation Solution
A method involving the formation of hard masks with a stack structure of pad oxide and nitride layers, etching to define grooves, depositing a gate conductive polysilicon layer with a sacrificial layer, and using CMP and wet etching processes to control layer thickness and prevent residue, ensuring stable process and improved device characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a thick nitride layer is used as hard mask to secure process margin, then manufacturing precision is improved, but the nitride layer and silicon pillar are likely to lean while conducting process
Solution Approach 1:
The hard mask is segmented into multiple thin nitride layers (first nitride layer and second nitride layer) deposited at different stages, replacing the conventional single thick nitride layer. This segmentation prevents leaning while maintaining sufficient process margin, as each thin layer is stable and the cumulative thickness provides the needed protection.
2Ease of manufacture
If polysilicon layer is deposited to fill space with great aspect ratio, then gate formation is completed, but voids are likely to be produced in the space
Solution Approach 1:
The polysilicon layer is deposited to a thickness that does not completely fill the groove space, leaving a partial fill condition. This prevents void formation by avoiding excessive deposition that would trap air or create discontinuities, while still providing sufficient gate material after subsequent processing steps.
3Ease of manufacture
If polysilicon layer for gate is deposited, then gate is formed, but polysilicon layer remains on sidewall of upper portion of silicon pillar causing short circuit
Solution Approach 1:
The polysilicon layer is selectively removed from the sidewalls of the upper portion of silicon pillars through etching processes. This extraction eliminates the source of potential short circuits between adjoining gates, while preserving the gate structure where needed.
Solution Approach 2:
The polysilicon layer is selectively removed only from specific locations (sidewalls of upper portions) while maintaining it in other critical areas. This local quality differentiation ensures that gates are isolated where necessary while maintaining functionality where required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method stabilizes the manufacturing process, prevents nitride layer and silicon pillar leaning, reduces etch loss, and avoids short circuits between gates, thereby enhancing the characteristics and reliability of semiconductor devices.
Implementation Method 1
forming a gate conductive layer on the hard masks including surfaces of the grooves to a thickness that does not fill the grooves; forming a sacrificial layer on the gate conductive layer to fill the grooves; removing a partial thickness of the sacrificial layer to expose the gate conductive layer
Implementation Method 2
removing portions of the gate conductive layer which are formed on the hard masks and on sidewalls of upper portions of the grooves; removing the remaining sacrificial layer
Data Source
AI summary
A method for manufacturing a semiconductor device having a vertical transistor includes forming hard masks on a semiconductor substrate to expose portions of the semiconductor substrate. Then the exposed portions of the semiconductor substrate are etched to define grooves in the semiconductor substrate. A gate conductive layer is formed on the hard masks and surfaces of the grooves to a thickness that does not completely fill the grooves. A sacrificial layer is formed on the gate conductive layer to completely fill the grooves. A partial thickness of the sacrificial layer is removed to expose the gate conductive layer and portions of the gate conductive layer formed on the hard masks and on sidewalls of upper portions of the grooves are removed. The remaining sacrificial layer is completely removed. Gates are formed on sidewalls of lower portions of the grooves by etching the gate conductive layer.