Multi-Layered Sidewall Spacer Gate Structure for Vertical Transistors
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Solution Overview
Problem
In the manufacturing of semiconductor devices, particularly vertical transistors, existing gate formation methods face challenges in achieving precise control over the size and positioning of gate structures due to limitations in patterning processes, which become more critical as device dimensions decrease.
Innovation Solution
A novel method involving the formation of a multi-layered sidewall spacer around a vertically oriented channel semiconductor structure, comprising a non-sacrificial high-k insulating innermost spacer, a sacrificial outermost spacer, and a non-sacrificial metal-containing second spacer, where the sacrificial outermost spacer is removed to define a replacement gate electrode cavity, allowing for the formation of a final conductive gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional patterning processes are used to define gate structures, then the manufacturing process remains simple, but the precision of gate size and positioning deteriorates as device dimensions decrease
Solution Approach 1:
The patent applies preliminary action by forming a multi-layered sidewall spacer structure before the gate electrode is created. The spacer layers (including sacrificial and non-sacrificial materials) are deposited and patterned in advance, establishing precise dimensional boundaries that will define the final gate structure. This preliminary framework enables accurate gate positioning without relying on subsequent high-precision patterning steps.
Solution Approach 2:
The patent uses intermediary materials in the form of sacrificial and non-sacrificial spacer layers that mediate between the channel structure and the final gate electrode. These intermediary spacers act as templates and placeholders during fabrication, enabling precise gate dimension control through their thickness and positioning rather than through direct patterning of the gate itself.
2Manufacturing precision
If multi-layered sidewall spacers with multiple deposition steps are formed, then gate structure precision is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent segments the gate formation process into multiple functional layers: a first non-sacrificial spacer layer, a sacrificial spacer layer, and a second non-sacrificial spacer layer. Each layer serves a specific purpose in defining gate dimensions and positioning. This segmentation allows independent optimization of each layer's properties and simplifies the overall control of gate geometry through cumulative layer thicknesses.
Solution Approach 2:
The patent employs parameter changes by varying the thickness, material composition, and deposition conditions of each spacer layer to achieve precise gate dimensions. By controlling parameters such as layer thickness through deposition time and rate, and selecting materials with different etch selectivities, the final gate structure dimensions are precisely tuned without requiring complex lithographic patterning.
Data Source
AI summary
One illustrative method disclosed herein includes forming a multi-layered sidewall spacer (MLSS) around a vertically oriented channel semiconductor structure, wherein the MLSS comprises a non-sacrificial innermost first spacer (a high-k insulating material), a sacrificial outermost spacer and at least one non-sacrificial second spacer (a metal-containing material) positioned between the innermost spacer and the outermost spacer, removing at least a portion of the sacrificial outermost spacer from the MLSS while leaving the at least one non-sacrificial second spacer and the non-sacrificial innermost first spacer in position and forming a final conductive gate electrode in place of the removed sacrificial outermost spacer.