Vertical Transistor Gate Stack Contact Insulation
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Solution Overview
Problem
Current semiconductor memory devices face challenges in enhancing integration and reliability, particularly in achieving high capacity data processing in miniaturized electronic products, where traditional planar transistor structures are inefficient.
Innovation Solution
A memory device with a vertical transistor structure is developed, featuring a substrate with a channel region and stacked gate electrode layers that define pad regions with a stepped structure, where contact plugs are electrically insulated and connected to the gate electrode layers, allowing for increased integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a planar transistor structure is used, then the device structure is simple and easy to manufacture, but the integration capacity and data processing capacity are insufficient
Solution Approach 1:
The patent transitions from a planar (2D) transistor structure to a vertical (3D) transistor structure by extending the channel region perpendicular to the substrate surface. This dimensional change allows multiple gate electrode layers to be stacked vertically, significantly increasing integration capacity and data processing capacity while maintaining manufacturability through established vertical fabrication processes
2Productivity
If multiple gate electrode layers are stacked to increase integration, then the integration capacity is enhanced, but the manufacturing precision and alignment difficulty increase
Solution Approach 1:
The patent divides the gate electrode structure into multiple discrete gate electrode layers (first gate electrode layer, second gate electrode layer, etc.) that are stacked vertically. Each layer can be independently formed and aligned, allowing for modular manufacturing that reduces the overall precision requirement compared to forming a single complex gate structure, while still achieving high integration capacity
3Reliability
If contact plugs penetrate through gate electrode layers to connect to lower layers, then the electrical connection is achieved, but the risk of electrical short circuit and reliability issues increases
Solution Approach 1:
The patent introduces an insulating layer as an intermediary between the first gate electrode layer and the second gate electrode layer in regions where contact plugs are formed. This insulating layer acts as a barrier that prevents direct electrical contact between adjacent gate electrode layers, eliminating the risk of short circuits while allowing contact plugs to penetrate through and establish electrical connections to lower layers
Data Source
AI summary
According to example embodiments, a memory device includes a substrate, a channel region on the substrate, a plurality of gate electrode layers stacked on each other on the substrate, and a plurality of contact plugs. The gate electrode layers are adjacent to the channel region and extend in one direction to define a pad region. The gate electrode layers include first and second gate electrode layers. The contact plugs are connected to the gate electrode layers in the pad region. At least one of the contact plugs is electrically insulated from the from the first gate electrode layer and electrically connected to the second gate electrode layer by penetrating through the first gate electrode layer.