Vertical Transistor Gate Stacking for High Integration Density
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing integration density and improving reliability, particularly in memory cell regions with conventional planar transistor structures.
Innovation Solution
A semiconductor device with a vertical transistor structure is proposed, featuring gate electrodes stacked in a staircase form, interlayer insulating layers, channel structures penetrating through gate electrodes, and a through-wiring region with sacrificial insulating layers and slit regions to enhance integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional planar transistor structure is used, then the device structure is simple to manufacture, but the integration density is low
Solution Approach 1:
The patent transitions from a planar (2D) transistor structure to a vertical (3D) transistor structure by stacking gate electrodes and channel structures in the thickness direction. This dimensional change allows multiple memory cells to be integrated within the same planar footprint, significantly increasing integration density while maintaining manufacturability through sequential layer deposition processes
2Productivity
If gate electrodes are stacked vertically to increase integration density, then more memory cells can be packed, but etching control and pad region definition become more difficult
Solution Approach 1:
The patent segments the gate electrode stack into multiple independently controllable gate electrodes (first, second, third gate electrodes) with different etching depths. By forming etching stop layers between these gate electrodes, the etching process can be precisely controlled to expose specific pad regions without affecting other areas, thereby achieving both high integration density and precise manufacturing control
Solution Approach 2:
The patent introduces etching stop layers as intermediary elements between the gate electrodes and the substrate. These stop layers act as mediators that control the etching depth and protect underlying structures, enabling precise definition of pad regions while maintaining the vertical stacking structure for high integration density
3Productivity
If the vertical transistor structure with stacked gate electrodes is implemented, then integration density improves, but the device structure becomes more complex
Solution Approach 1:
The patent designs the vertical transistor structure where stacked gate electrodes serve multiple functions: they act as control gates for memory cells, provide etching stop layers for process control, and define pad regions for electrical connections. This multi-functionality reduces the need for separate structural elements, thereby increasing integration density without proportionally increasing device complexity
Data Source
AI summary
A semiconductor device includes gate electrodes stacked to be spaced apart from each other on a substrate in a first direction, extending in a second direction, and including pad regions bent in a third direction, sacrificial insulating layers extending from the gate electrodes to be stacked alternately with the interlayer insulating layers, separation regions penetrating through the gate electrodes, extending in the second direction, and spaced apart from each other to be parallel to each other, and a through-wiring region spaced apart from the separation regions to overlap the pad regions between the separation regions adjacent to each other and including contact plugs penetrating through the pad regions. The through-wiring region includes slit regions, and each of the slit regions is disposed to penetrate through the sacrificial insulating layers on one side of a respective pad region.