Vertical Transistor Gate Surrounding Channel for Density
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Solution Overview
Problem
Conventional transistors in semiconductor devices face a short channel effect due to miniaturization, leading to decreased On current, and existing vertical transistors lack effective control over channel structures.
Innovation Solution
A vertical transistor design with eight controlling surfaces is implemented, featuring a substrate, semiconductor structure with two vertical plates and a bottom plate, a gate that surrounds and fills the space between the plates, and a buried conductive region, along with a gate dielectric layer and conductive layer, to enhance control and density in chip arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If physical dimensions of transistors are continuously reduced to accelerate operating speed and meet miniaturization demands, then operating speed increases and device size decreases, but short channel effect occurs and On current decreases
Solution Approach 1:
The patent transitions from conventional planar transistors to vertical transistors by changing the dimensional orientation of the channel from horizontal to vertical. The semiconductor structure extends vertically from the substrate with the gate wrapping around the channel in three dimensions, providing enhanced control over the charge carrier flow while maintaining miniaturized footprint. This dimensional change allows continued scaling without suffering from short channel effects that plague planar transistors at small dimensions.
2Reliability
If conventional horizontal transistors are replaced by vertical transistors to resolve short channel effect, then channel control improves, but device complexity increases due to three-dimensional structure
Solution Approach 1:
The gate structure is designed to wrap around and surround the vertical channel, with the gate dielectric layer nested between the gate and the semiconductor channel. This nested configuration allows the gate to control the channel from multiple directions (top, bottom, and sidewalls) simultaneously, providing superior electrostatic control compared to planar gates while maintaining a compact vertical footprint.
Solution Approach 2:
The patent employs a composite gate dielectric layer structure consisting of multiple materials (such as silicon oxide, silicon nitride, and silicon oxynitride) deposited in sequential layers. This composite dielectric structure provides optimized electrical properties including better interface quality, reduced leakage, and enhanced gate control, while managing the complexity through systematic material integration.
3Reliability
If vertical transistor structure with gate surrounding semiconductor structure is implemented, then channel control is enhanced with eight controlling surfaces, but manufacturing precision requirements increase
Solution Approach 1:
The manufacturing process employs preliminary patterning and sacrificial layer techniques to pre-establish the vertical semiconductor structures before forming the gate. By preparing the channel structures, isolation regions, and contact holes in advance with precise alignment, the subsequent gate deposition and formation can proceed with reduced complexity. The sacrificial layers are removed after defining the vertical structures, enabling precise gate placement without requiring extremely tight process windows.
4Quantity of substance
If array with vertical transistors is designed to increase device density, then chip area occupancy is reduced, but manufacturing process complexity increases
Solution Approach 1:
The vertical transistor structure serves multiple functions simultaneously: the vertical channel provides high-density packing, the surrounding gate delivers enhanced control, the wrapped gate structure enables multi-directional electrostatic control, and the vertical orientation allows for three-dimensional integration. This multi-functionality in a single structure achieves high device density without requiring separate specialized components for each function, thereby managing manufacturing complexity.
Data Source
AI summary
A vertical transistor includes a substrate, a semiconductor structure, a gate, a gate dielectric layer, and a conductive layer. The semiconductor structure is disposed on the substrate and includes two vertical plates and a bottom plate. The bottom plate has an upper surface connected to bottoms of the two vertical plates and a bottom surface connected to the substrate. The gate surrounds the semiconductor structure to fill between the two vertical plates, and the gate is disposed around the two vertical plates. The gate dielectric layer is sandwiched in between the gate and the semiconductor structure, and the conductive layer is disposed on the semiconductor structure and electrically connected with tops of the two vertical plates.