Vertical Transistor Electric Field Buffering for GIDL Reduction
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Solution Overview
Problem
Vertical transistors experience significant gate-induced drain leakage (GIDL) due to the floating channel, which is exacerbated by the high electric field concentrated at the gate-drain boundary, leading to increased leakage current and reduced channel mobility.
Innovation Solution
Incorporation of an electric field-buffering region with a band gap different from the pillar material, positioned at the drain overlapped with the gate, and a work function-controlling layer to reduce the work function difference between the gate and drain, thereby mitigating the GIDL and leakage current. This is achieved by using materials like Ge, SiGe, GaAs, or SiC for the electric field-buffering region and forming additional electric field-buffering regions at the source and drain edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a vertical transistor with a floating channel is used to achieve high integration, then the area is reduced, but gate-induced drain leakage (GIDL) increases due to high electric field concentration at the gate-drain boundary
Solution Approach 1:
An electric field-buffering region is introduced as an intermediary layer between the drain and the gate-drain boundary. This region, formed with a different band gap material (e.g., Ge, SiGe, GaAs, or SiC), acts as a mediator that buffers the high electric field concentration, thereby reducing GIDL while preserving the compact vertical transistor structure
Solution Approach 2:
The electric field-buffering region is selectively positioned only at the gate-drain overlap area where the high electric field concentration occurs. This localized modification addresses the specific problem of GIDL without affecting the overall device performance or requiring changes to the entire transistor structure
2Ease of manufacture
If a work function difference exists between the gate and drain, then the transistor can be formed with standard materials, but leakage current increases due to the work function difference
Solution Approach 1:
The band gap parameter of the material at the gate-drain boundary is changed by introducing an electric field-buffering region with a different band gap material. This parameter change increases the work function of the drain region, narrowing the work function difference between gate and drain, thereby reducing leakage current while maintaining ease of manufacture through selective material deposition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the leakage current and GIDL by increasing the work function of the drain and narrowing the work function difference between the gate and drain, while maintaining channel mobility by positioning the electric field-buffering regions only at the gate-drain overlap, thus enhancing the performance of vertical transistors.
Implementation Method 1
The electric field-buffering region may have a band gap different from a band gap of a material in the pillar
Implementation Method 2
The work function-controlling layer may be formed in at least one of the first junction region and the second junction region overlapped with the gate to decrease a difference between a work function of the first junction region and a work function of the second junction region
Data Source
AI summary
A vertical transistor may include a pillar, a gate and an electric field-buffering region. The pillar may be vertically extended from a surface of a semiconductor substrate. The pillar may include a source, a channel region and a drain. The gate may be formed on an outer surface of the pillar. The gate may be overlapped with the channel region, a portion of the source configured to make contact with the channel region, and a portion of the drain configured to make contact with the channel region. The electric field-buffering region may be formed in the portion of the drain overlapped with the gate. The electric field-buffering region may have a band gap different from a band gap of a material in the pillar.