Vertical Transistor Halo Pocket Mitigates Short Channel Effects

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As technology nodes shrink, vertical transistor devices face increased short channel effects due to reduced gate thickness, leading to decreased yield and integrated density of semiconductor circuits.

Innovation Solution

A vertical transistor device with a substrate having a protruding portion and a doping region of a different conductivity type formed beneath it, along with a gate dielectric and gate electrode structure, analogous to a halo pocket structure, to mitigate short channel effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the gate thickness is reduced to shrink technology nodes, then the lateral size of transistor element decreases and integrated density increases, but short channel effect is triggered and yield decreases

Engineering Contradiction:
Improvegate thicknessVSAvoidyield
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent introduces a doping region with a second conductivity type beneath the protruding portion and adjacent to the source, creating a localized doping structure (halo pocket) with specific doping concentration (about 1×10^13 cm^-3). This local modification of electrical properties mitigates short channel effect without requiring overall device redesign, allowing continued scaling while maintaining yield

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent transitions from planar transistor architecture to a vertical transistor structure with a protruding portion extending upward from the substrate. The gate electrode is disposed adjacent to the sidewall of the protruding portion, creating a vertical channel. This dimensional change allows the channel length to be defined by the protruding portion height rather than lateral gate dimensions, enabling continued scaling in the lateral plane while maintaining adequate channel length for reliability

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If the gate thickness is reduced to shrink technology nodes, then the lateral size of transistor element decreases and integrated density increases, but short channel effect is triggered

Engineering Contradiction:
Improvelateral size of transistor elementVSAvoidshort channel effect
Core Design Contradiction:
Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The halo pocket doping region is introduced locally beneath the protruding portion with a doping concentration of about 1×10^13 cm^-3, which is substantially greater than the substrate but substantially less than the source. This localized doping creates an electrical field that counteracts the short channel effect, allowing the transistor to maintain proper electrical characteristics despite reduced lateral dimensions

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

By moving to a vertical transistor architecture where the channel extends vertically from the substrate surface through the protruding portion, the patent decouples the lateral transistor footprint from the channel length. The channel length is now determined by the protruding portion height, allowing lateral size to be minimized for high integration density while maintaining sufficient channel length to prevent short channel effect

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9496390B2Vertical transistor device with halo pocket contacting source
Publication Date: 2016.11.15 UNITED MICROELECTRONICS CORP
  • US9496390B2 patent drawing
  • US9496390B2 patent drawing
  • US9496390B2 patent drawing

AI summary

A vertical transistor device comprises a substrate, a first source, a drain, a first gate dielectric layer, a first gate electrode and a first doping region. The substrate has at least one protruding portion. The first source having a first conductivity type is formed on the substrate. The drain having the first conductivity type is disposed on the protruding portion. The first gate electrode is disposed adjacent to a first sidewall of the protruding portion. The first gate dielectric layer is disposed between the first gate electrode and the first sidewall as well as being disposed adjacent to the first source and the drain. The first doping region having a second conductivity type is formed beneath the protruding portion and adjacent to the first source.