Vertical Transistor Cylindrical Channel Hot Carrier Control
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Solution Overview
Problem
The miniaturization of transistors leads to worsening hot carrier effects due to increased electric fields, causing performance degradation and susceptibility to short channel and punch-through effects, which are difficult to control with existing LDD structures.
Innovation Solution
A vertical transistor structure with a cylindrical channel region and controlled ion implantation processes, including hydrogen annealing and selective epitaxial growth, to manage the hot carrier effect and extend the effective channel length, thereby reducing the short channel effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor channel length is reduced for miniaturization, then integration density is improved, but hot carrier effects worsen due to increased electric fields
Solution Approach 1:
The patent transitions from a planar transistor structure to a vertical transistor structure where the channel extends in the vertical dimension rather than horizontally. This dimensional change allows the channel length to be extended vertically, reducing the horizontal electric field strength while maintaining compact footprint for high integration density.
Solution Approach 2:
The patent modifies the channel orientation parameter from horizontal to vertical, and adjusts the electric field distribution by changing the channel length and cross-sectional area parameters. This enables reduced electric field strength in the horizontal direction while maintaining adequate channel length for performance.
2Object-affected harmful factors
If LDD structure is used to reduce electric field, then hot carrier effect is mitigated, but short channel effect increases due to dopant diffusion
Solution Approach 1:
The vertical channel structure changes the geometry such that the LDD region is positioned differently relative to the channel. The vertical orientation reduces the lateral diffusion path of dopants into the channel, mitigating the short channel effect while maintaining the electric field reduction benefits of LDD.
3Productivity
If channel length is reduced for scaling, then device density is improved, but punch-through effect susceptibility increases
Solution Approach 1:
By extending the channel vertically rather than horizontally, the patent achieves adequate channel length for punch-through prevention without increasing the horizontal footprint. The vertical channel provides sufficient length to prevent carrier punch-through while maintaining compact device dimensions for high density.
4Manufacturing precision
If threshold voltage control is attempted with ion implantation, then transistor switching is improved, but process complexity increases due to multiple implantation steps
Solution Approach 1:
The patent applies ion implantation selectively to specific regions (source/drain regions adjacent to the vertical channel) rather than uniformly across the device. This localized approach achieves threshold voltage control and channel doping with reduced process complexity compared to multiple implantation steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical transistor structure effectively controls the hot carrier effect and prevents performance degradation, enabling larger scale integration while maintaining transistor performance.
Implementation Method 1
a gate insulation layer formed over the source region, a side of the channel region, and the drain region
Implementation Method 2
a source region having a concentration of implanted impurity ions on a semiconductor substrate
Data Source
AI summary
A transistor which may effectively control the short channel effect with a vertical transistor structure. This structure may prevent the degradation of a transistor's performance caused by the hot carrier effect. The transistor has a source region having a concentration of implanted impurity ions on a semiconductor substrate; a channel region having a cylindrical shape over the source region; a drain region formed over the channel region; a gate insulation layer formed over the source region, a side of the channel region, and the drain region; and a gate conductor extending over an upper portion and one side of the channel region.