Vertical Transistor Structure for Lithography-Limited IC Scaling
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Solution Overview
Problem
The scaling of multi-gate and nanowire transistors in integrated circuits poses challenges due to constraints on lithographic processes, particularly in maintaining critical dimension and spacing, and there is a need for improved high bandwidth computing solutions.
Innovation Solution
The development of integrated circuit structures with vertical transistors, including a cup-shaped design with channel material wrap-around, and the implementation of backside power delivery to reduce power network resistance and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-gate and nanowire transistors are scaled down to increase device density, then the number of functional units on the chip increases, but the constraints on lithographic processes become overwhelming and the trade-off between critical dimension and spacing deteriorates
Solution Approach 1:
The patent transitions from planar transistor architecture to vertical transistor architecture, moving the device structure into the third dimension. The vertical transistor extends in the vertical direction with source and drain regions at different heights, allowing channel formation in multiple directions (e.g., four-sided channel wrapping around the gate). This dimensional change enables higher device density without proportionally increasing lithographic complexity, as the vertical structure can be formed using existing lithographic processes combined with selective epitaxial growth and etching techniques.
2Quantity of substance
If transistor size is shrunk to increase the number of memory or logic devices on a chip, then capacity increases, but the necessity to optimize the performance of each device becomes increasingly significant
Solution Approach 1:
The vertical transistor structure provides enhanced gate control over the channel through multi-directional wrapping (e.g., tri-gate or tetra-gate configurations), improving short-channel control and device performance. The vertical architecture allows for better electrostatic control and higher drive current per device, enabling each shrunk transistor to maintain or improve performance despite size reduction.
Solution Approach 2:
The patent implements selective epitaxial growth to form channel regions with different crystal orientations and properties in different locations. Specifically, <110> oriented channel regions are formed in certain areas while <100> oriented channel regions are formed in other areas, allowing optimization of carrier mobility and device performance in different regions of the vertical transistor structure.
3Ease of manufacture
If conventional tri-gate fabrication process is used on bulk silicon substrates, then lower cost and less complicated process are achieved, but maintaining mobility improvement and short channel control below 10 nanometer node becomes challenging
Solution Approach 1:
The patent segments the channel formation process into distinct stages: first forming a sacrificial nanowire structure, then selectively removing portions to create the multi-sided channel geometry, and finally forming the gate structure. This segmentation allows the complex vertical transistor structure to be built using a series of simpler, well-controlled process steps rather than attempting to form the entire structure in one operation.
Solution Approach 2:
The patent uses a sacrificial nanowire structure as an intermediary element during fabrication. The nanowire is first formed using standard lithographic and epitaxial processes, then selectively etched or removed to create the desired channel geometry, and finally the gate is formed around the remaining structure. This intermediary approach simplifies the overall fabrication process by breaking down the complex vertical transistor formation into manageable steps.
Data Source
AI summary
Structures having vertical transistors are described. In an example, an integrated circuit structure includes a channel structure on a drain contact layer, the channel structure having an opening extending there through. A gate dielectric layer is on a bottom and along sides of the opening, the gate dielectric layer laterally surrounded by the channel structure. A gate electrode is on and laterally surrounded by the gate dielectric layer. A source contact layer is on sides of a portion of the gate dielectric layer extending above the channel structure.