Vertical Transistor Integration Density Leakage
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Solution Overview
Problem
Conventional planar cell transistors in semiconductor memory devices face challenges with short channel effects and high power consumption due to gate widths of 40 nanometers or less, leading to channel leakage currents, which hinder increased integration density without performance degradation.
Innovation Solution
The use of vertical transistors with a drain, channel, and source regions stacked in a semiconductor substrate, along with gate electrodes on the sidewalls of the channel regions, allows for increased integration density without performance degradation by employing active pillars and capacitors in trenches, enabling multi-bit cell operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the gate width of planar cell transistor is reduced to 40 nanometers or less to increase integration density, then integration density is improved, but channel leakage current increases causing high power consumption
Solution Approach 1:
The patent transitions from planar transistors to vertical transistors, changing the device architecture from two-dimensional to three-dimensional. The vertical transistor structure stacks the source region, channel region, and drain region vertically, with gate electrodes wrapping around the channel region sidewalls. This dimensional change allows for shorter channel lengths without proportionally reducing gate control, thereby reducing channel leakage current while maintaining high integration density.
2Loss of energy
If vertical transistors are employed to reduce channel leakage current and power consumption, then power consumption is reduced, but device structure becomes more complex
Solution Approach 1:
The patent merges multiple functions into the vertical transistor structure. The wrapped gate electrodes simultaneously provide gate control and sidewall coverage, the vertical stacking integrates source-channel-drain regions in a compact footprint, and the shared bit line structure consolidates multiple transistor outputs. This merging approach reduces overall device complexity despite the three-dimensional architecture.
Solution Approach 2:
The vertical transistor structure serves multiple functions: the wrapped gate electrodes provide both gate control and sidewall protection, the vertical stacking achieves high integration density while maintaining electrical performance, and the shared bit line structure enables multi-bit cell operations. This multi-functionality reduces the need for separate components, thereby managing device complexity.
3Loss of energy
If vertical transistors with wrapped gate electrodes are used to improve gate control and reduce leakage, then channel leakage current is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent employs preliminary actions in the fabrication process by forming the channel region and source/drain regions in a specific vertical sequence before adding the wrapped gate electrodes. The gate electrodes are deposited and patterned in stages, with each stage preparing the structure for the next. This preliminary structuring simplifies the overall manufacturing process by establishing a robust foundation before adding complex three-dimensional features.
Data Source
AI summary
A semiconductor device includes a first capacitor in a trench of a semiconductor substrate and an active pillar disposed on the semiconductor substrate opposite the first capacitor. The active pillar includes first region, first channel region, second region, second channel region and third region, sequentially stacked. A pillar connection pattern electrically connects the first capacitor to a first source region. A first gate electrode is disposed on a sidewall of the first channel region. A common drain region is disposed in the second region, and a common bit line is disposed on a sidewall of the common drain region. A second gate electrode is disposed on a sidewall of the second channel region, and a second source region is disposed in the third region. A second capacitor is disposed on a top surface of the second source region opposite the second channel region.