Vertical Transistor Inverter with Shared Gate Electrodes
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Solution Overview
Problem
Current CMOS inverter circuits face challenges in achieving tight pitch, low power dissipation, and simple wiring due to limitations in transistor configuration and fabrication methods, particularly with vertical field-effect transistors (VFETs).
Innovation Solution
The development of CMOS inverter circuits using VFETs with shared gate electrodes and epitaxially formed semiconductor fins, allowing for close device placement and efficient power management through specific fabrication steps such as epitaxial growth, gate dielectric layer formation, and metal gate deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional planar MOSFETs are used in CMOS inverter circuits, then the wiring and configuration are simple, but the pitch cannot be reduced further and power dissipation remains high
Solution Approach 1:
The patent transitions from planar MOSFETs to vertical field-effect transistors (VFETs), changing the current flow direction from in-plane to vertical (normal to the die surface). This dimensional change enables tight pitch by stacking transistors vertically, allowing closer device placement while maintaining electrical isolation through the vertical architecture.
Solution Approach 2:
The patent merges the gate electrodes of the p-type and n-type VFETs into a single shared gate structure. This merging simplifies the wiring configuration by reducing the number of separate gate connections needed, while the vertical architecture maintains electrical isolation between the p-type and n-type regions through the shared gate and substrate isolation.
2Area of stationary object
If transistor dimensions are reduced to achieve tight pitch, then device density increases, but power dissipation increases due to reduced capacitance and resistance
Solution Approach 1:
By transitioning to vertical transistors, the patent achieves tight pitch through vertical stacking rather than lateral shrinking. This allows reduced device area while maintaining appropriate capacitance and resistance values through the vertical channel architecture, thereby controlling power dissipation while increasing device density.
3Ease of operation
If separate gate electrodes are used for p-type and n-type transistors, then each transistor can be independently controlled, but wiring complexity increases
Solution Approach 1:
The patent combines the gate electrodes of the p-type and n-type VFETs into a single shared gate structure that controls both transistors simultaneously. This merging simplifies wiring by reducing the number of gate connections from two separate lines to one shared line, while the vertical architecture and substrate isolation maintain proper electrical control of each transistor type.
4Length of moving object
If vertical field-effect transistors are implemented with shared gate electrodes, then tight pitch and simplified wiring are achieved, but fabrication complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct phases: forming p-type and n-type regions with electrical isolation, epitaxially growing semiconductor fins on each region, selectively removing fins, forming shared gate electrodes, and creating drain regions. This segmentation manages fabrication complexity by breaking down the complex vertical structure formation into manageable, sequential steps.
Solution Approach 2:
The patent performs preliminary actions by first forming the p-type and n-type regions with electrical isolation and epitaxially growing the semiconductor fins before forming the shared gate electrodes. This preliminary preparation simplifies subsequent fabrication steps by having the vertical structures ready to receive the shared gate, reducing overall fabrication complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables tight pitch, low inverter power dissipation, and simplified wiring of input, output, and power supply lines, while being compatible with CMOS processing, thereby enhancing density scaling and device performance.
Implementation Method 1
vertical field-effect transistors (VFETs) have configurations wherein the current between the drain and source regions is substantially normal to the surface of the die
Implementation Method 2
First and second semiconductor fins are epitaxially formed on the monolithic structure and within the dummy gate
Data Source
AI summary
CMOS inverters including gate-all-around vertical transistors are fabricated without requiring center gate contacts, thereby allowing close positioning of the transistors. The gate contact and the drain contact of the transistors are shared. Wiring of inverter input, output and power supply lines is simplified.