Vertical Transistor Late Epitaxy for Sharp Symmetric Junctions
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Solution Overview
Problem
VFET devices face challenges in precisely controlling gate length and producing sharp, symmetric channel-to-source/drain junctions due to the difficulty in controlling dopant diffusion and high substrate volume, leading to variability and high resistance in conventional fabrication methods.
Innovation Solution
The use of a late source/drain epitaxy process with sacrificial layers allows for the growth of epitaxy on pristine {100} planes, enabling simultaneous formation of symmetric, sharp channel-to-source/drain junctions with reduced thermal budget and minimizing resistance variability by growing top and bottom source/drain regions at the end of the fabrication flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional bottom source/drain epitaxy is grown in the substrate followed by thermal diffusion, then source/drain regions are formed, but the dopant species must diffuse a long distance through the substrate resulting in difficult control of channel-to-source/drain junction definition and high bottom source/drain resistance
Solution Approach 1:
The bottom source/drain epitaxy is grown preliminarily in the substrate between the vertical fin channels before the fin structures are fully formed. This preliminary positioning allows the epitaxial material to be in close proximity to the future channel region, eliminating the need for long-distance thermal diffusion and enabling precise junction definition while reducing resistance
Solution Approach 2:
The conventional thermal diffusion process is replaced with an epitaxial growth process. Instead of relying on thermal diffusion to transport dopant species through the substrate, the source/drain regions are formed through controlled epitaxial growth of semiconductor material, providing superior control over junction definition and reducing resistance
2Manufacturing precision
If late source/drain epitaxy is used to grow epitaxy on pristine {100} planes, then symmetric sharp channel-to-source/drain junctions are formed with reduced thermal budget, but the fabrication process complexity increases
Solution Approach 1:
Sacrificial layers are deposited preliminarily at the bottom and top of the fin channel structures before the source/drain epitaxy is grown. These sacrificial layers define the precise locations where source/drain regions will form, enabling symmetric sharp junctions to be created when the epitaxial growth occurs on the pristine {100} crystal planes
Solution Approach 2:
The fabrication process utilizes parameter changes in the epitaxial growth conditions, specifically growing the source/drain regions on pristine {100} crystal planes with controlled orientation. This parameter control enables the formation of symmetric sharp junctions while managing the thermal budget through precise temperature and time control during the late epitaxy step
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved device performance by forming uniform, symmetric junctions with reduced variability and lower resistance, enhancing the precision and reliability of VFET devices.
Implementation Method 1
growth of epitaxy on pristine {100} planes, enabling simultaneous formation of symmetric, sharp channel-to-source/drain junctions
Implementation Method 2
followed by a thermally-driven diffusion of the dopant species
Data Source
AI summary
VFET devices having symmetric, sharp channel-to-source/drain junctions and techniques for fabrication thereof using a late source/drain epitaxy process are provided. In one aspect, a VFET device includes: at least one vertical fin channel disposed on a substrate; a gate stack alongside the at least one vertical fin channel; a bottom source/drain region directly below the at least one vertical fin channel having, for example, an inverted T-shape with a flat bottom; and a top source/drain region over the at least one vertical fin channel. A method of fabricating a VFET device is also provided.