Vertical Multi-Channel Transistor Structure for Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional transistor structures face challenges in reducing standby current (Ioff) and leakage current, particularly as device dimensions are scaled down, leading to increased complexity in aligning source/drain edges with the gate structure and controlling the effective channel length, which affects performance in achieving Tera-Scale Integration (TSI) goals.
Innovation Solution
A 3D transistor structure with a convex semiconductor body featuring multiple upward extending conductive channels and a trench filled with a gate conductive layer, surrounded by a gate dielectric, which eliminates shallow trench isolation regions between the channels, allowing for improved alignment and reduced leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional FinFET or Tri-gate structures are used to scale down device dimensions, then integration capacity increases, but leakage current (Ioff) increases and manufacturing precision deteriorates
Solution Approach 1:
The patent transitions from planar 2D channel structures to 3D vertical nanowire bodies, moving the conduction path into the third dimension. Multiple nanowires extend vertically from the substrate, with gate structures wrapping around them, creating a three-dimensional transistor architecture that improves gate control and reduces leakage while maintaining scalability for high integration.
Solution Approach 2:
The semiconductor body is divided into multiple discrete nanowire segments rather than a single continuous structure. Each nanowire acts as an independent conduction channel, allowing parallel current flow through multiple pathways. This segmentation enables better control over leakage current while maintaining high conduction capacity when the transistor is ON.
2Area of stationary object
If device dimensions are scaled down to reduce transistor area, then integration density improves, but alignment precision between source/drain edges and gate structure becomes more difficult
Solution Approach 1:
The invention moves from two-dimensional planar geometry to three-dimensional vertical nanowire structures. The nanowires extend perpendicular to the substrate surface, allowing the gate to wrap around them in multiple directions. This vertical dimension provides inherent alignment tolerance, as the gate can effectively contact the nanowire along its entire length rather than requiring precise edge-to-edge alignment in a single plane.
Solution Approach 2:
The transistor structure combines multiple materials with different properties: silicon nanowires for conduction, high-k dielectric materials for gate insulation, and metal gates for control. This composite approach allows optimization of each material's properties independently, with the nanowire providing robust vertical conduction paths that are less sensitive to lateral alignment variations.
3Speed
If effective channel length is reduced to improve switching speed, then transistor performance improves, but leakage current control becomes more difficult
Solution Approach 1:
The patent extends the channel in the vertical dimension through nanowire growth, allowing the effective channel length to be defined by the nanowire height rather than lateral distance. The gate wraps around the nanowire, providing control along the entire vertical channel length. This vertical configuration enables shorter lateral dimensions for faster switching while maintaining adequate vertical channel length for leakage control through the wrapped gate structure.
Solution Approach 2:
The wrapped gate structure performs multiple functions simultaneously: it controls the channel conduction, provides electrical isolation between adjacent nanowires, and defines the effective channel length. This multi-functional gate design enables independent optimization of switching speed and leakage control without requiring separate structural elements.
Data Source
AI summary
A transistor structure includes a semiconductor body, a source region, a drain region and a gate region. The semiconductor body has a convex structure and the convex structure has at least four conductive channels extending upward. The source region contacts with a first end of the convex structure. The drain region contacts with a second end of the convex structure. The gate region has a gate conductive layer, wherein the gate conductive layer is across over the convex structure. Two or four conductive channels are not parallel to each other, and there is no shallow trench isolation region among the at least four conductive channels.