Self-aligned Vertical Transistor Local Interconnect Metallization
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Solution Overview
Problem
The metallization of vertical field effect transistors (FETs) is challenging due to their unique vertical design, which complicates the formation of electrical connections between source regions and metal gates, hindering efficient scaling and packing density.
Innovation Solution
A metallization scheme is developed that forms lower-level local interconnects connecting source regions at the bottom of semiconductor fins and upper-level interconnects connecting adjacent metal gates along the sidewalls of channel regions, allowing for electrical connections and forming gate, source, and drain contact structures on the same side of vertical FETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical FET design is used to increase packing density, then scaling limit is improved, but metallization difficulty increases
Solution Approach 1:
The patent divides the interconnection structure into two distinct levels: lower-level local interconnects that contact source regions at the bottom of fins, and upper-level interconnects that contact metal gates along sidewalls. This segmentation allows each level to be optimized independently for its specific contact requirements, resolving the metallization difficulty while preserving the vertical design's packing density advantages
Solution Approach 2:
The patent transitions from traditional planar interconnection to a three-dimensional vertical interconnection architecture. By forming interconnects that contact regions at different vertical levels (bottom source regions and sidewall metal gates), the solution exploits the vertical dimension to simplify metallization routing while maintaining high packing density
2Productivity
If vertical FET architecture is implemented, then scaling beyond lateral FETs is improved, but electrical connection formation becomes difficult
Solution Approach 1:
The electrical connection system is segmented into lower-level local interconnects for source region contact and upper-level interconnects for metal gate contact. This segmentation enables independent optimization of each connection path, making electrical connection formation feasible in vertical architecture while preserving scaling benefits
Solution Approach 2:
The patent introduces intermediate interconnect structures that facilitate electrical connections to vertically-oriented regions. The lower-level local interconnects serve as intermediaries to contact bottom source regions, while upper-level interconnects intermediate the connection to sidewall metal gates, resolving the electrical connection formation difficulty
Data Source
AI summary
A metallization scheme for vertical field effect transistors (FETs) is provided. By forming lower-level local interconnects connecting source regions located at bottom portions of semiconductor fins, and upper-level interconnects connecting adjacent metal gates located along sidewalls of channel regions of the semiconductor fins, electrical connections to the source regions and the metal gates can be provided through the lower-level local interconnects and the upper-level local interconnects, respectively. As a result, gate, source and drain contact structures are formed on the same side of vertical FETs.