Localized Gate Dielectric in Vertical Thin Film Transistors

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Solution Overview

Problem

Vertical transistor device architectures face challenges in reducing footprint and controlling threshold voltage variation due to lateral scaling issues and material thickness variations, particularly in vertical thin film transistor structures for memory devices like vertical Fe-NAND flash memory.

Innovation Solution

An additive nanopatterning technique is employed to localize gate dielectric material on the channel portion of vertical transistors, reducing aspect ratios and material thickness variations, and allowing for better control of threshold voltage levels by selectively depositing gate dielectric material only where necessary, thereby minimizing unnecessary build-up on adjacent structural features.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If blanket deposited material layers are used to form vertical transistor structures, then the structure can be formed with standard deposition processes, but device variation increases and footprint cannot be reduced below 20 nm

Engineering Contradiction:

Improvedevice dimension controlVSAvoiddevice footprint

Core Design Contradiction:

Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The gate dielectric material is selectively deposited only on the channel portion of the vertical transistor structure, not on the entire sidewall. This localized deposition approach allows precise control of the gate dielectric thickness where it is needed for device operation, while avoiding unnecessary material buildup elsewhere, thereby enabling footprint reduction below 20 nm without compromising device uniformity

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The sidewall surface is segmented into functional regions: the channel portion requiring gate dielectric and the non-channel portions where gate dielectric is avoided. This segmentation is achieved through selective deposition techniques that deposit material only on specific surface regions, allowing independent optimization of each region's properties and reducing overall device footprint

Inventive Principle:

Principle #1Segmentation

2Reliability

If gate dielectric material is deposited on all sidewall surfaces, then complete coverage is achieved, but unnecessary material buildup increases device variation and complicates threshold voltage control

Engineering Contradiction:

Improvethreshold voltage controlVSAvoidmaterial thickness uniformity

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

Gate dielectric material is deposited with spatial selectivity, applying the insulating layer only to the channel portion where electrical control is required. This localized approach ensures uniform thickness control in the functional region while avoiding variable thickness buildup in non-functional regions, thereby improving threshold voltage control and reducing device variation

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

A masking layer or selective deposition technique acts as an intermediary to control where gate dielectric material is deposited. This intermediary mechanism enables precise spatial control of material placement, ensuring gate dielectric is formed only on the channel portion and preventing unwanted deposition on adjacent structures, thus maintaining material thickness uniformity

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves threshold voltage control and reduces device dimension variability, enabling more precise dimensional scaling and efficient operation of vertical thin film transistor structures, particularly in memory devices.

Implementation Method 1

Methodology Applied

Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS11139401B2Vertical thin film transistor structures with localized gate dielectric

Publication Date: 2021.10.05 SK HYNIX NAND PRODUCT SOLUTIONS CORP

AI summary

Transistor structures with a deposited channel semiconductor material may have a vertical structure that includes a gate dielectric material that is localized to a sidewall of a gate electrode material layer. With localized gate dielectric material threshold voltage variation across a plurality of vertical transistor structures, such as a NAND flash memory string, may be reduced. A via may be formed through a material stack, exposing a sidewall of the gate electrode material layer and sidewalls of the dielectric material layers. A sidewall of the gate electrode material layer may be recessed selectively from the sidewalls of the dielectric material layers. A gate dielectric material, such as a ferroelectric material, may be selectively deposited upon the recessed gate electrode material layer, for example at least partially backfilling the recess. A semiconductor material may be deposited on sidewalls of the dielectric material layers and on the localized gate dielectric material.