Vertical Transistor Structure for Low-Capacitance Miniaturization
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Solution Overview
Problem
Existing semiconductor devices face challenges in miniaturization, integration, parasitic capacitance, wiring load, and reliability, while demanding higher density and faster operation.
Innovation Solution
A semiconductor device with a vertical transistor structure, utilizing a first and second insulating layer with conductive layers and a semiconductor layer, allowing for reduced occupation area and precise channel length control, and incorporating a low dielectric constant material to minimize parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a conventional planar transistor structure is used, then the device area is large, but the integration density is low
Solution Approach 1:
The patent transitions from a planar two-dimensional transistor structure to a vertical three-dimensional structure. The channel extends vertically through multiple insulating layers rather than laterally in a single plane, enabling higher integration density while reducing the footprint area occupied by each transistor.
Solution Approach 2:
The transistor structure embeds multiple functional layers within each other vertically. The semiconductor layer is nested between first and second insulating layers, with conductive layers and gate structures nested within the insulating layers, creating a compact stacked configuration that reduces overall device area.
2Quantity of substance
If conventional transistor structures are used, then the wiring load is high, but the signal transmission speed is slow
Solution Approach 1:
The patent extracts and eliminates unnecessary wiring by integrating control functions directly into the vertical transistor structure. The gate electrodes and conductive layers are positioned to provide direct vertical control, removing the need for extensive lateral wiring connections and reducing overall wiring load while improving signal transmission efficiency.
3Object-generated harmful factors
If conventional transistor structures are used, then the parasitic capacitance is high, but the electrical characteristics are poor
Solution Approach 1:
The patent introduces insulating layers as intermediary materials between conductive elements and the semiconductor channel. These insulating layers act as mediators that electrically isolate adjacent conductive structures, reducing parasitic capacitance between them while maintaining proper electrical control over the semiconductor channel through the vertical gate structure.
Data Source
AI summary
A semiconductor device that can be easily miniaturized is provided. A semiconductor device with reduced parasitic capacitance is provided. The semiconductor device includes a transistor, a first insulating layer, and a second insulating layer. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer. The first insulating layer is positioned above the first conductive layer and includes a first opening reaching the first conductive layer. The second conductive layer is positioned above the first insulating layer. The semiconductor layer is in contact with the second conductive layer and a side surface of the first insulating layer and a top surface of the first conductive layer in the first opening. The third insulating layer is in contact with a top surface of the first insulating layer and the semiconductor layer in the first opening. The second insulating layer is positioned above the third insulating layer and includes a second opening reaching the third insulating layer in a position overlapping the first opening. The third conductive layer is provided to fill the second opening and the first opening.