Vertical Transistor Memory Array for High-Density DRAM
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Solution Overview
Problem
The challenge in semiconductor memory arrays is to achieve a high-density 4F2 DRAM memory array structure with vertical transistors that has good substrate contact and a simple fabrication process, while overcoming the short-channel effect and channel floating issues associated with horizontal and conventional vertical transistors.
Innovation Solution
A memory array structure with vertical transistors is designed, featuring a semiconductor pillar with a gate structure on its side wall, source and drain regions located at the upper and lower ends, and a substrate contact formed by a doped region connected to the body line, which allows for effective channel length increase and improved isolation between transistors, reducing the area of the memory cell and simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a horizontal transistor structure is used, then the fabrication process is simple, but the channel length cannot be increased effectively leading to short-channel effect
Solution Approach 1:
The patent transitions from a horizontal transistor structure to a vertical transistor structure, changing the spatial dimension of the channel from lateral to vertical. This allows the channel length to be extended in the vertical direction (z-axis) while maintaining a compact footprint in the planar direction, thereby overcoming the short-channel effect without complicating the fabrication process excessively.
2Reliability
If the bit line is offset to form substrate contact, then substrate contact is achieved, but the distance to adjacent transistor decreases causing isolation issues and crosstalk
Solution Approach 1:
The patent segments the substrate contact formation process by creating separate contact holes for different transistors. Each substrate contact is independently formed through dedicated contact holes, allowing proper spacing and isolation between adjacent transistors while ensuring effective substrate contact for each device, thereby preventing crosstalk.
3Reliability
If a vertical transistor structure is used, then the channel length can be increased to overcome short-channel effect, but substrate contact becomes difficult to realize
Solution Approach 1:
The patent performs preliminary action by forming the substrate contact holes and filling them with conductive material before completing the vertical transistor structure. This preliminary substrate contact formation simplifies the overall manufacturing process by establishing the contact path early, avoiding the need for complex subsequent steps to access the substrate contact point.
4Productivity
If the feature size is scaled down to increase integration level, then more memory cells fit in the same area, but the short-channel effect becomes more serious
Solution Approach 1:
The patent employs vertical transistors that extend in the z-direction, allowing the channel length to be increased vertically while the planar footprint remains small. This enables high integration density in the x-y plane while maintaining sufficient channel length through vertical extension, thereby achieving both high productivity and reliable transistor operation.
Data Source
AI summary
A memory array structure and a method for forming the same are provided. The memory array structure comprises: a substrate; a plurality of memory cells, each memory cell including a vertical transistor, of which a gate structure is formed in a first trench extending in a first direction; a plurality of word lines in the first direction, each word line formed in the first trench; a plurality of bit lines in a second direction, each bit line formed in lower sides of a semiconductor pillars; a plurality of body lines in the first direction, each body line having a first portion formed on the gate electrodes and a second portion covering a part of a top surface of semiconductor pillar for providing a substrate contact to vertical channel regions; and a plurality of data storage device contacts.