Vertical Transistor Devices for Memory Scalability
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Solution Overview
Problem
Conventional transistors face limitations in scalability, particularly in memory applications, where they struggle to maintain performance and efficiency.
Innovation Solution
The development of vertical transistor devices, which include a semiconductor substrate with transistors formed in multiple layers, featuring a channel and source/drain contacts between the channel and substrate, along with a gate dielectric and gate electrode, allowing for improved scalability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional transistors are used in memory applications, then manufacturing process is simpler, but scalability is limited
Solution Approach 1:
The patent transitions from planar transistors to vertical transistors, utilizing the third dimension (vertical stacking) to improve scalability. The vertical transistor structure includes a channel extending vertically from the substrate, with source/drain contacts at different heights, enabling higher density memory arrays without increasing lateral footprint.
2Productivity
If vertical transistor structures are implemented, then scalability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The vertical transistor structure is segmented into distinct functional regions: substrate, channel, gate dielectric, gate electrode, and source/drain contacts at different levels. This segmentation allows for standardized manufacturing processes for each layer, improving overall manufacturing precision despite the increased vertical complexity.
Solution Approach 2:
The patent employs preliminary patterning and alignment steps during fabrication to establish precise vertical stacking sequences. Gate dielectric and gate electrode layers are deposited and patterned before final source/drain contact formation, ensuring proper alignment and reducing manufacturing precision requirements in subsequent steps.
Data Source
AI summary
Disclosed herein are vertical transistor devices and techniques. In some embodiments, a device may include: a semiconductor substrate; a first transistor in a first layer on the semiconductor substrate; and a second transistor in a second layer, wherein the second transistor includes a first source/drain (S/D) contact and a second S/D contact, the first layer is between the second layer and the semiconductor substrate, and the first S/D contact is between the second S/D contact and the first layer. In some embodiments, a device may include: a semiconductor substrate; and a transistor above the semiconductor substrate, wherein the transistor includes a channel and a source/drain (S/D) contact between the channel and the semiconductor substrate.