Vertical Transistor Memory Arrays for Higher Density and Simpler Interconnects
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Solution Overview
Problem
Planar memory cells face challenges in scaling due to limitations in process technology, circuit design, and fabrication processes, leading to a ceiling in memory density.
Innovation Solution
The implementation of 3D memory architecture using vertical transistors, where a memory cell array with vertical transistors is bonded face-to-face with peripheral circuits, allowing for increased memory density and reduced chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology and fabrication processes, then memory density is improved, but as feature sizes approach a lower limit, planar process and fabrication techniques become challenging and costly, and memory density approaches an upper limit
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) vertical transistor architecture. The vertical transistor structure extends the channel in the vertical direction rather than laterally, enabling continued scaling of memory density without further reducing lateral feature sizes. This dimensional change allows memory cells to be stacked vertically, effectively increasing storage capacity while avoiding the fabrication challenges associated with further planar scaling.
2Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density is improved, but process technology and fabrication processes become more challenging and costly
Solution Approach 1:
By moving to vertical transistors, the patent enables memory density improvement through vertical stacking rather than lateral shrinking. This approach uses established fabrication processes to create vertical structures, avoiding the need for increasingly complex and costly advanced planar process technology. The vertical architecture allows memory cells to be formed using conventional process nodes while achieving higher density through the third dimension.
3Quantity of substance
If 3D memory architecture is implemented with vertical transistors, then memory density is enhanced and chip size is reduced, but new fabrication processes for vertical structures are required
Solution Approach 1:
The patent divides the memory device into separate semiconductor structures that are subsequently bonded together. The vertical transistors are formed in one structure, while peripheral circuits are formed in another. This segmentation allows each structure to be optimized independently and simplifies the overall fabrication process by enabling modular manufacturing and assembly, reducing the complexity of creating complete 3D memory devices in a single process flow.
Data Source
AI summary
In certain aspects, a three-dimensional (3D) memory device includes a second semiconductor structure. The second semiconductor structure includes an array of memory cells, each of the memory cells including a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor, a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction, and a plurality of word lines coupled to the memory cells and each extending in a third direction perpendicular to the first direction and the second direction. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with one side of the semiconductor body in the second direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction.