Vertical Transistor Memory Cells for Higher Density and Lower Leakage
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Solution Overview
Problem
Planar memory cells face challenges in scaling due to increased complexity and cost as feature sizes approach limits, leading to density constraints and high leakage currents, which are not effectively addressed by conventional fabrication techniques.
Innovation Solution
The implementation of vertical transistors replaces conventional planar transistors in memory devices, allowing for reduced transistor area, simplified interconnect structures, and increased memory cell density through multi-gate and single-gate configurations, enabling better channel control and reduced leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar transistors are used in memory cells, then fabrication processes are well-established, but memory cell area is large and leakage current is high
Solution Approach 1:
The patent transitions from planar (2D) transistors to vertical (3D) transistors by extending the channel in the vertical direction through substrate thinning and forming semiconductor bodies that protrude from the substrate surface. This dimensional change reduces the lateral footprint of each memory cell while maintaining effective channel length for current control.
Solution Approach 2:
The patent segments the transistor structure into distinct vertical components: source/drain regions at the substrate level, vertical channel bodies extending upward, and gate structures wrapping around the channels. This segmentation allows independent optimization of each component and enables better packing density.
2Productivity
If feature sizes are reduced in planar memory cells, then memory density increases, but fabrication complexity and cost increase significantly
Solution Approach 1:
By moving to vertical transistors, the patent achieves higher memory density without proportionally increasing fabrication complexity. The vertical architecture allows standard planar fabrication steps to be combined with selective substrate thinning and vertical structure formation, avoiding the need for entirely new complex process flows required for scaled planar devices.
Solution Approach 2:
The patent changes the critical dimension from lateral feature size to vertical structure height. This parameter change allows memory density to be increased by controlling vertical dimensions through substrate thinning depth and semiconductor body height, which can be achieved through established etching and deposition techniques rather than requiring advanced lithographic scaling.
3Device complexity
If planar transistors are used, then interconnect structures are complex, but vertical transistors simplify interconnect architecture
Solution Approach 1:
The vertical transistor architecture repositions the channel and active regions in the vertical dimension, allowing bit lines and word lines to be routed more efficiently in the lateral plane. This reduces the number of interconnect layers and via levels required compared to planar structures where all connections must be made in the same lateral plane.
4Reliability
If conventional planar structures are used, then leakage current control is poor, but vertical structures improve channel control and reduce leakage
Solution Approach 1:
The patent utilizes a phase transition in the fabrication process by transforming the substrate from a thick bulk structure to a thinned structure with protruding semiconductor bodies. This structural phase transition enables the gate to wrap around the channel in multiple dimensions, providing superior electrostatic control and reducing off-state leakage current through better field effect modulation.
Data Source
AI summary
In certain aspects, a memory device includes a semiconductor layer, a peripheral circuit including a peripheral transistor in contact with the semiconductor layer, an array of memory cells disposed beside the semiconductor layer and the peripheral circuit, and bit lines coupled to the memory cells. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. Each of the bit lines extends in a second direction perpendicular to the first direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction.