Vertical Transistor Memory Structure with Doped Layer
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Solution Overview
Problem
Current memory structures face challenges in enhancing electrical performance without increasing the size of memory cells, particularly in achieving effective device integration by replacing horizontal transistors with vertical ones.
Innovation Solution
A memory structure featuring a vertical transistor with specific layers such as a first source/drain layer, channel pillar, gate, gate dielectric layer, doped layer, spacer layer, and second source/drain layer, where the doped layer is disposed between the source/drain and gate layers to prevent hole accumulation and guide them out, improving the floating-body effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If horizontal transistors are used in memory structures, then device integration degree is limited, but layout area of memory cell is larger
Solution Approach 1:
The patent transitions from horizontal transistor layout to vertical transistor architecture, utilizing the third dimension (vertical direction) to achieve higher device integration density while reducing the planar footprint of memory cells. The vertical channel structure extends the transistor height in the Z-direction, allowing more devices to be packed into the same XY-plane area.
2Productivity
If vertical transistors are introduced to save layout area, then device integration degree increases, but hole accumulation between source/drain and gate layers occurs
Solution Approach 1:
The patent introduces a doped layer as an intermediary component between the source/drain layer and the gate in vertical transistors. This doped layer acts as a mediator to facilitate hole extraction and prevent harmful hole accumulation, thereby maintaining the benefits of vertical transistor integration without suffering from the hole accumulation problem.
Solution Approach 2:
The patent converts the potentially harmful hole accumulation effect into a beneficial floating-body effect by carefully controlling the doping characteristics of the doped layer. The accumulated holes in the doped layer create a positive body effect that enhances transistor switching performance and threshold voltage control, transforming a problem into an advantage.
3Area of stationary object
If vertical transistor structure is implemented, then layout area is reduced, but floating-body effect control becomes challenging
Solution Approach 1:
The patent controls the floating-body effect by adjusting key parameters of the doped layer, including doping concentration, doping type, and layer thickness. By optimizing these parameters, the patent achieves effective control over hole accumulation and floating-body effects while maintaining the compact vertical transistor structure.
Data Source
AI summary
Provided are a memory structure and a method for manufacturing the same. The memory structure includes a capacitor and a transistor disposed thereon and electrically connected thereto. The transistor includes a first and a source/drain layers, a channel pillar, a gate, a gate dielectric layer, a doped layer, and a spacer layer. The first source/drain layer is electrically connected to the capacitor. The channel pillar is on the first source/drain layer. The gate is on a sidewall of the channel pillar. The gate dielectric layer is between the gate and the channel pillar. The doped layer is on the sidewall of the channel pillar and above the gate. The spacer layer is between the gate and the first source/drain layer and between the gate and the doped layer. The second source/drain layer is on or in the channel pillar.