Vertical Transistor Layout for High-Density Memory Current Drive
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Solution Overview
Problem
The challenge in the development of semiconductor devices, particularly in memory cells, is the reduction of transistor size to increase storage density while maintaining or improving performance, including driver current and manufacturing accuracy.
Innovation Solution
A vertical transistor design is proposed, featuring a source electrode on a substrate, a drain electrode stacked above the source electrode, and a gate electrode and semiconductor layer in the same layer, positioned between the source and drain electrodes. The semiconductor layer includes two spaced-apart layers with the gate electrode between them, allowing simultaneous electric field application to enhance on-state current and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the transistor size is reduced to increase storage density, then the storage density increases, but the driver current and manufacturing accuracy deteriorate
Solution Approach 1:
The patent transitions from a conventional planar transistor structure to a vertical transistor structure, utilizing the vertical dimension (third dimension) to achieve higher storage density. The source electrode, drain electrode, and gate electrode are stacked vertically, allowing transistors to be arranged in three-dimensional space rather than confined to a two-dimensional plane, thereby increasing storage density without compromising driver current or manufacturing accuracy.
Solution Approach 2:
The semiconductor layer is divided into multiple segments (first semiconductor layer, second semiconductor layer, third semiconductor layer) stacked vertically. Each segment can be independently controlled by corresponding gate electrodes, allowing for optimized current flow and improved driver current performance while maintaining compact size for high storage density.
2Quantity of substance
If the transistor size is reduced to increase storage density, then the storage density increases, but the manufacturing accuracy deteriorates
Solution Approach 1:
By moving to a vertical structure, the patent reduces the lateral footprint of each transistor while maintaining adequate vertical spacing and electrode dimensions for accurate manufacturing. The vertical stacking allows for larger electrode areas in the vertical direction, which can be more easily manufactured with precision compared to reducing lateral dimensions.
Solution Approach 2:
The patent employs a nested structure where the gate electrode is positioned between the source and drain electrodes, and multiple semiconductor layers are nested vertically. This nested arrangement optimizes space utilization and maintains clear manufacturing boundaries for each component, improving manufacturing accuracy while achieving high storage density.
3Ease of manufacture
If the conventional planar transistor structure is used, then the manufacturing process is simpler, but the on-state current and driving performance are insufficient
Solution Approach 1:
The vertical structure increases the effective channel area and improves charge carrier transport by utilizing vertical electric fields, resulting in higher on-state current and driving performance. The vertical stacking of source, drain, and gate electrodes creates more efficient current flow paths compared to planar structures.
Solution Approach 2:
The gate electrode is positioned between the source and drain electrodes in the vertical stacking sequence, allowing the gate to exert preliminary control over the channel formation before current flows from source to drain. This configuration enhances the gate's ability to modulate the channel and improve on-state current performance.
Data Source
AI summary
A vertical transistor, and a memory cell and a manufacturing method therefor are provided. The vertical transistor includes: a source electrode disposed on a substrate; a drain electrode which is disposed at a side, away from the substrate, of the source electrode; and a gate electrode and a semiconductor layer, which are in the same layer, and are disposed between the source electrode and the drain electrode in a first direction which is perpendicular to the substrate. The gate electrode at least comprises a column-shaped first gate electrode extending in the first direction. The semiconductor layer comprises a first semiconductor layer and a second semiconductor layer which are in the same layer and spaced apart from each other, and the first gate electrode is disposed between the first semiconductor layer and the second semiconductor layer.