Vertical Transistor Arrays for High-Density Memory Integration
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Solution Overview
Problem
Current nonvolatile memory devices, such as NAND-type flash memories, face challenges in achieving high integration levels and low power consumption while maintaining fast random access read times and high capacity, particularly in embedded and mass storage applications.
Innovation Solution
The development of integrated circuit memory devices with a vertical stack of independently controllable gate electrodes, including semiconductor channel regions, charge storage layers, and electrically insulating layers, which allows for efficient data storage and retrieval through a U-shaped wrap-around charge storage layer configuration, enabling higher integration and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical integration techniques are used in NAND-type flash memories, then integration levels and capacity are improved, but device complexity increases
Solution Approach 1:
The patent transitions from planar to vertical transistor architecture, stacking multiple gate electrodes (CG1, CG2, CG3) and charge storage layers (NS1, NS2, NS3) vertically along the channel region. This dimensional change enables higher integration levels by utilizing the vertical space above the substrate, effectively increasing storage capacity without proportionally increasing device footprint or complexity
Solution Approach 2:
The patent implements a nested structure where charge storage layers (NS1, NS2, NS3) are positioned between and around gate electrodes (CG1, CG2, CG3) in a stacked configuration. Each charge storage layer is enclosed by insulating layers and positioned relative to specific gate electrodes, creating a nested arrangement that maximizes space utilization and enables multiple storage nodes within a compact vertical structure
2Quantity of substance
If vertical integration techniques are used in NAND-type flash memories, then capacity is improved, but power consumption increases
Solution Approach 1:
By stacking gate electrodes and charge storage layers vertically, the patent increases storage capacity within the same footprint without requiring proportional increases in operating voltage or current. The vertical architecture allows independent control of each memory cell through its dedicated gate electrodes, enabling selective access and reducing overall power consumption compared to expanded planar designs
Solution Approach 2:
The patent divides the memory structure into independently controllable segments with separate gate electrodes (CG1, CG2, CG3) for each memory cell. This segmentation allows selective activation of individual cells or groups of cells, enabling random access operations without powering the entire array, thereby reducing power consumption while maintaining high capacity
3Speed
If vertical transistor arrays with independently controllable gate electrodes are implemented, then fast random access read times are achieved, but device complexity increases
Solution Approach 1:
The vertical stacking of independently controllable gate electrodes enables three-dimensional addressing schemes that facilitate fast random access to specific memory cells without scanning through entire rows or columns. Each gate electrode can be independently controlled to select specific cells, dramatically reducing access time despite the increased vertical structural complexity
Solution Approach 2:
By providing independent gate electrodes for each memory cell, the patent enables fine-grained control and selective access to individual cells or small groups of cells. This segmentation allows the memory system to directly access any cell without sequential scanning, achieving fast random access read times while managing complexity through modular cell design
Data Source
AI summary
An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.