Vertical Transistor Memory Cell Metal Gate Design
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Solution Overview
Problem
Conventional memory cells with vertical transistors and capacitors face issues of high gate resistance and energy loss at high operating frequencies due to structural compactness and silicon nitride residue, leading to power consumption and open circuit problems.
Innovation Solution
A memory cell design featuring a metal gate with a doped polysilicon layer interposed between the gate dielectric and metal gate, along with a trench structure that includes a trench top oxide layer and a capacitor at the bottom, to reduce gate resistance and improve electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a doped polysilicon layer is deposited from sidewalls to central region of deep trench, then the gate structure is formed, but the structure at central region becomes less compact causing high resistance in gate
Solution Approach 1:
The patent changes the material parameter from doped polysilicon to metal for the gate electrode, which fundamentally alters the electrical resistance parameter. Metal materials inherently provide lower resistance compared to doped polysilicon, directly resolving the high gate resistance issue without requiring structural modifications.
Solution Approach 2:
The patent employs a composite structure consisting of metal gate electrode combined with gate dielectric layer and interfacial layers. This composite material approach allows optimization of electrical properties (low resistance) while maintaining structural integrity and compactness within the deep trench configuration.
2Reliability
If isotropic etching is used to form collar silicon nitride, then the sidewalls are covered, but silicon nitride residue accumulates at central region causing open circuits
Solution Approach 1:
The patent completely removes the collar silicon nitride layer that causes residue accumulation problems. By eliminating this intermediate protective layer, the source of silicon nitride residue is removed, preventing open circuit issues without requiring complex residue removal processes.
Solution Approach 2:
Instead of using isotropic etching to form collar silicon nitride and then dealing with residue removal, the patent inverts the approach by directly forming the metal gate structure without the intermediate silicon nitride collar, thereby eliminating the residue problem from the outset.
3Area of stationary object
If deep trench capacitor structure is used, then device size is reduced, but gate resistance increases and energy loss occurs at high operating frequency
Solution Approach 1:
The patent changes the gate material parameter from high-resistance doped polysilicon to low-resistance metal, which directly reduces power consumption and energy loss at high operating frequencies while preserving the compact deep trench capacitor structure.
Solution Approach 2:
The patent creates a composite gate structure with metal electrode and gate dielectric that maintains the vertical integration benefits for size reduction while the metal component provides low resistance for reduced power consumption at high frequencies.
Data Source
AI summary
Memory cells with vertical transistor and capacitor and fabrication methods thereof. The memory cell comprises a substrate with a trench. A capacitor is disposed at the bottom of the trench. A first conductive layer is electrically coupled to the capacitor. The first conductive layer is isolated the substrate by a collar dielectric layer. A trench top oxide (TTO) layer is disposed on the first conductive layer. A vertical transistor is disposed over the TTO layer. The vertical transistor comprises a gate dielectric layer disposed on the sidewalls of the upper portion of the trench, and a metal gate disposed in the upper portion of the trench.