Vertical Storage Transistor Memory Layout Without Bit Line Contact Holes
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Solution Overview
Problem
The limitation of existing semiconductor manufacturing technologies in reducing the size of storage transistors due to the resolution constraints of lithography devices, which prevents further improvement in integration density and leads to short-channel effects.
Innovation Solution
The implementation of a manufacturing method for integrated circuit memory that forms a vertical storage transistor in the overlapping region of intersecting bit and word lines, eliminating the need for a bit line contact hole and allowing for a smaller unit configuration size, thereby reducing the overall memory size and improving arrangement flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography-based manufacturing is used, then manufacturing precision is limited by lithography resolution, but device complexity and process steps remain manageable
Solution Approach 1:
The patent transitions from planar (2D) transistor architecture to vertical (3D) transistor architecture. The vertical storage transistor extends in the depth direction perpendicular to the substrate, utilizing the third dimension to achieve smaller footprint while maintaining or improving functionality. This dimensional change allows bypassing lithography resolution limits that constrain planar feature sizes.
Solution Approach 2:
The vertical storage transistor is formed within the overlapping region of the bit line and word line, effectively nesting the transistor structure within the conductive line intersection. The transistor channel extends vertically through the conductive lines, with the source and drain regions positioned at different heights, creating a compact nested configuration that eliminates the need for separate contact holes.
2Productivity
If vertical storage transistor is formed in overlapping region of bit line and word line, then integration density improves and unit size reduces, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the formation of the vertical storage transistor with the existing bit line and word line patterning processes. The transistor is formed in the overlapping region where the bit line and word line intersect, combining multiple structural elements into a single integrated formation step. This merging approach utilizes the already-patterned conductive lines as part of the transistor structure, reducing the need for additional separate processing steps.
Solution Approach 2:
The overlapping region of the bit line and word line serves multiple functions: it acts as both the conductive interconnect structure and the region for forming the vertical storage transistor. The bit line and word line materials also serve as the source/drain and gate structures of the transistor, respectively, eliminating the need for separate contact holes and reducing process steps.
3Area of stationary object
If storage transistor size is reduced below lithography limit, then integration density improves, but manufacturing precision deteriorates due to lithography constraints
Solution Approach 1:
The patent achieves smaller unit configuration size by transitioning to vertical transistor architecture where the channel extends in the depth direction. This allows the transistor to occupy less area on the substrate plane while maintaining adequate channel length for proper functionality. The vertical extension bypasses lithography resolution limits that constrain planar feature sizes, enabling continued scaling of unit cell area.
Solution Approach 2:
The patent changes the geometric parameters of the transistor from planar dimensions to vertical dimensions. Instead of reducing the channel width and length in the plane (which are constrained by lithography), the channel length is extended in the vertical direction. This parameter transformation allows achieving smaller footprint without being limited by lithography resolution, as the critical vertical dimensions can be controlled by deposition and etching processes rather than photolithography.
Data Source
AI summary
A manufacturing method of an integrated circuit memory includes: a substrate is provided; a bit line extending along a first direction is formed on the substrate; a word line extending along a second direction is formed on the bit line; and a vertical storage transistor is formed in an overlapping region where the word line and the bit line are spatially intersected, the vertical storage transistor being located on the bit line, and connected to the bit line.