Vertical Transistor Devices for Memory Scalability
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Solution Overview
Problem
Conventional transistors face limitations in scalability, particularly in memory applications, where they struggle to maintain performance and efficiency.
Innovation Solution
The development of vertical transistor devices, which include a semiconductor substrate with transistors formed in multiple layers, featuring a channel and source/drain contacts, and a gate dielectric and gate electrode that surround the channel, allowing for improved scalability and performance through specific manufacturing techniques such as thin film deposition and patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional transistors are used in memory applications, then manufacturing process is simpler, but scalability is limited
Solution Approach 1:
The patent transitions from planar transistors to vertical transistors, utilizing the third dimension (vertical stacking) to improve scalability. The vertical transistor structure includes a channel extending vertically from the substrate, with gate electrodes wrapping around the channel, enabling higher density integration while maintaining manufacturability through adapted fabrication processes
2Productivity
If vertical transistor structure is implemented, then scalability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The vertical transistor structure is divided into distinct functional segments: substrate, channel, gate dielectric, and gate electrode layers. Each segment is formed through separate fabrication steps, allowing optimized processing for each component while maintaining overall manufacturing feasibility through modular construction
Solution Approach 2:
The patent employs preliminary patterning and deposition steps to prepare the substrate and form underlying structures before creating the vertical transistor components. This sequential preparation ensures that each subsequent step builds on a precisely prepared foundation, reducing precision requirements for later high-precision operations
Data Source
AI summary
Disclosed herein are vertical transistor devices and techniques. In some embodiments, a device may include: a semiconductor substrate; a first transistor in a first layer on the semiconductor substrate; and a second transistor in a second layer, wherein the second transistor includes a first source/drain (S/D) contact and a second S/D contact, the first layer is between the second layer and the semiconductor substrate, and the first S/D contact is between the second S/D contact and the first layer. In some embodiments, a device may include: a semiconductor substrate; and a transistor above the semiconductor substrate, wherein the transistor includes a channel and a source/drain (S/D) contact between the channel and the semiconductor substrate.