Vertical Transistor Memory Architecture for Higher Density Scaling
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Solution Overview
Problem
Planar memory cells face challenges in scaling due to increased complexity and cost as feature sizes approach a lower limit, limiting memory density.
Innovation Solution
Implementing a 3D memory architecture with vertical transistors and a face-to-face bonding interface between semiconductor structures, allowing for a stacked arrangement of memory cells and peripheral circuits, which reduces transistor area and simplifies interconnect structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but fabrication complexity and cost increase
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) stacked architecture. Memory cells are arranged in multiple tiers stacked vertically, with each tier containing memory cells and peripheral circuits. This vertical stacking enables significantly higher memory density without further reducing lateral feature sizes, thereby avoiding the associated fabrication complexity and cost increases.
2Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density is improved, but feature sizes approach a lower limit making planar process challenging
Solution Approach 1:
By stacking memory cell tiers vertically in the third dimension, the patent achieves higher memory density without requiring further reduction of lateral feature sizes. This approach maintains manufacturing precision requirements at achievable levels while still increasing overall memory capacity through vertical integration of multiple tiers.
3Quantity of substance
If 3D memory architecture with vertical transistors is implemented, then memory cell density is improved and fabrication complexity is reduced, but new manufacturing processes are required
Solution Approach 1:
The patent divides the memory device into multiple discrete tiers, each comprising memory cells and peripheral circuits formed on separate substrates. These tiers are subsequently stacked and bonded together. This segmentation allows each tier to be manufactured using relatively standard processes, while the overall 3D architecture achieves high density. The modular tiered structure makes the manufacturing process more manageable despite the complexity of vertical integration.
Data Source
AI summary
In certain aspects, a memory device includes a memory cell including a vertical transistor, and a storage unit having a first end coupled to a first terminal of the vertical transistor. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The memory device also includes a metal bit line coupled to a second terminal of the vertical transistor via an ohmic contact and extending in a second direction perpendicular to the first direction. The memory device further includes a dielectric layer opposing the memory cell with the metal bit line positioned between the dielectric layer and the memory cell. The memory device further includes a conductor extending from the dielectric layer to couple to a second end of the storage unit.