Vertical Transistor Metallization Layout for Low-RDS(on) Packaging
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Solution Overview
Problem
Vertical transistor devices face challenges in packaging due to the need for electrical connections on opposing surfaces, which complicates the achievement of low drain to source resistance (RDS(on)) in chip-sized packages using wafer level chip scale packaging techniques.
Innovation Solution
A semiconductor device with a vertical transistor configuration featuring a source electrode, drain electrode, and gate electrode, where a metallization structure on one surface includes source, drain, and gate pads, and a conductive structure with an electrically insulating layer on the opposing surface, allowing for direct electrical insulation and reduced packaging complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertical transistor devices use opposing surfaces for drain and source contacts to achieve low RDS(on), then electrical performance is improved, but packaging complexity increases due to the need for connections on both sides
Solution Approach 1:
The patent applies dimensionality change by moving all external electrical contacts (source, drain, and gate pads) to a single surface of the semiconductor die through conductive vias. This redistributes the electrical connections from three-dimensional opposing surfaces to a two-dimensional single-surface layout, enabling wafer-level chip-scale packaging while preserving the vertical transistor structure's low RDS(on) performance.
2Ease of manufacture
If through silicon vias are used to couple drain region to drain contact on opposing surface, then electrical connection is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent applies preliminary action by forming conductive vias and metallization structures during the semiconductor fabrication process before die attachment. This preliminary preparation of electrical pathways enables subsequent simple die bonding without requiring complex post-packaging via formation or backside routing, reducing overall manufacturing complexity.
3Volume of moving object
If chip-sized packages are used to reduce size, then compactness is improved, but achieving low RDS(on) becomes more difficult due to connection constraints
Solution Approach 1:
The patent maintains low RDS(on) in chip-sized packages by keeping the vertical transistor structure intact with current flow through the bulk semiconductor material, while using conductive vias to bring all contacts to one surface. This separates the electrical performance function (vertical current path) from the packaging function (single-surface contacts), enabling both compact size and low resistance.
Data Source
AI summary
A semiconductor device includes a semiconductor die having a vertical transistor device with a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a second surface opposing the first surface. A first metallization structure is located on the first surface and includes at least one source pad coupled to the source electrode, at least one drain pad coupled to the drain electrode and at least one gate pad coupled to the gate electrode, A second metallization structure is electrically insulated from the semiconductor die by the electrically insulating layer.