Vertical Oxide-Semiconductor Transistor With Reduced Miller Capacitance
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Solution Overview
Problem
Current horizontal oxide-semiconductor transistors are too large to meet the requirements of high-end display devices, which demand high resolution and faster response speeds, and they also face limitations in reducing loading capacitance.
Innovation Solution
A vertical oxide-semiconductor transistor design with a smaller gate overlapping area between the gate and source/drain, which reduces Miller capacitance and increases response speed, is proposed. This design includes an insulating substrate, a source, a gate that surrounds the source, an oxide-semiconductor layer, and a drain that completely overlaps the source and partially overlaps the gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If horizontal oxide-semiconductor transistor design is used, then the transistor can be manufactured with conventional processes, but the transistor area is too large for high-resolution display devices
Solution Approach 1:
The patent transitions from a planar horizontal transistor design to a vertical transistor architecture, utilizing the third dimension (vertical stacking) to reduce the footprint area. The channel extends vertically from the source through the gate to the drain, enabling compact integration while maintaining manufacturing feasibility through adapted deposition and etching processes.
2Speed
If gate overlapping area with source/drain is increased, then the transistor can be simplified in structure, but the Miller capacitance increases and response speed decreases
Solution Approach 1:
The patent employs a vertical gate structure that wraps around the channel in the vertical dimension, minimizing horizontal overlap with source and drain regions. This vertical configuration reduces the overlapping area and associated Miller capacitance while maintaining effective gate control through the vertical channel extension.
Solution Approach 2:
The gate structure is designed to surround and wrap around the vertical channel, creating a nested configuration where the gate encloses the channel region. This nested architecture provides comprehensive gate control over the channel while minimizing parasitic overlap capacitances with the source and drain terminals.
3Area of moving object
If vertical channel design is implemented, then the transistor area is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The vertical transistor structure is divided into distinct segmented layers including source, gate, oxide-semiconductor channel, and drain regions arranged vertically. Each layer is formed through separate deposition and patterning steps, allowing independent optimization and simplifying the overall manufacturing process despite the vertical architecture.
Solution Approach 2:
The patent employs preliminary patterning and deposition steps to pre-form the vertical channel structure and gate regions before final assembly. By preparing the vertical stack in advance with proper alignment and positioning, the subsequent manufacturing steps are simplified, making the vertical design more manufacturable.
Data Source
AI summary
A vertical oxide-semiconductor transistor is proposed by the present invention, including an insulating substrate, a source in the insulating substrate, a gate on the insulating substrate, wherein the gate surrounds the source and forms a recess on the source, an inner spacer on an inner sidewall of the gate in the recess, an oxide-semiconductor layer on the inner spacer and the source and directly contacts the source, a filling oxide on the oxide-semiconductor layer and filling in the recess, and a drain on the oxide-semiconductor layer and filling oxide and directly connecting with the oxide-semiconductor layer, wherein the drain completely covers the source and partially overlaps the gate.