Vertical Transistor Multi-Doped Source-Drain Regions
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Solution Overview
Problem
Existing integrated circuit devices face challenges in reducing power consumption while maintaining high ON current and preventing short-circuiting and gate-induced drain leakage (GIDL) in resistance-variable storage devices.
Innovation Solution
The integrated circuit device incorporates a semiconductor member with specific conductivity type portions and impurity concentration profiles, including n+ and n− portions, to optimize impurity distribution and reduce resistance, thereby minimizing power consumption and GIDL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If high impurity concentration is used in source/drain regions to reduce resistance and power consumption, then power consumption is reduced, but short-circuiting and gate-induced drain leakage (GIDL) occur
Solution Approach 1:
The patent applies local quality by creating distinct impurity concentration zones within the source/drain regions. Specifically, it forms a first doped region with high impurity concentration adjacent to the channel for low resistance, and a second doped region with lower impurity concentration at the interface with the gate electrode to prevent GIDL. This spatial variation in impurity concentration allows simultaneous optimization of power consumption and reliability.
Solution Approach 2:
The source/drain regions are segmented into multiple doped regions with different impurity concentrations. The patent divides each source/drain region into at least two zones: a first doped region with higher impurity concentration and a second doped region with lower impurity concentration. This segmentation enables independent optimization of electrical resistance and leakage prevention in different spatial locations.
2Reliability
If multi-doping regions are implemented to prevent short-circuiting and GIDL, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent changes the impurity concentration parameter spatially within the source/drain regions to achieve both reliability improvement and manageable complexity. By varying the impurity concentration from high in the first doped region to lower in the second doped region, the patent prevents short-circuiting and GIDL while maintaining a relatively simple overall device structure that can be fabricated using standard semiconductor processing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces OFF current by preventing short-circuiting and GIDL, while ensuring a high ON current, thus achieving low power consumption in resistance-variable storage devices.
Implementation Method 1
a first semiconductor portion of a first conductivity type connected to the first wiring, a second semiconductor portion of the first conductivity type in which a concentration of a first impurity is lower than a concentration of the first impurity of the first semiconductor portion, a third semiconductor portion of the first conductivity type in which the concentration of the first impurity is higher than a concentration of the first impurity of the second semiconductor portion
Data Source
AI summary
An integrated circuit device includes a first wiring, a second wiring, a semiconductor member that is connected between the first and second wirings, an electrode, and an insulating film that is provided between the semiconductor member and the electrode. The semiconductor member includes a first semiconductor portion of a first conductivity type connected to the first wiring, a second semiconductor portion of the first conductivity type, a third semiconductor portion of the first conductivity type, a fourth semiconductor portion of the first conductivity type, a fifth semiconductor portion of a second conductivity type, and a sixth semiconductor portion of the first conductivity type in this order. A first edge of the electrode on a side of the first wiring overlaps the second, third, or fourth semiconductor portions.