Vertical Transistor Channel Structure for High-Density Panel Driving
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Solution Overview
Problem
The challenge lies in developing transistors with a vertical structure that can achieve high integration, ultra-high resolution, and increased operating margin while maintaining high driving current, without degrading performance and reducing the size of non-active areas, which is complicated by processing difficulties and limitations in reducing transistor size.
Innovation Solution
A transistor with a vertical structure is designed, featuring a channel area that is non-parallel to the substrate, with a gate insulating film having varying thicknesses and a reverse tapered insulation pattern, allowing for a short channel and high S-factor, and an active layer that directly contacts electrodes, enabling efficient current drive and reduced device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor size is reduced to increase integration, then integration density is improved, but processing difficulty increases and performance degrades
Solution Approach 1:
The patent transitions from a planar transistor structure to a vertical structure where the channel extends in the vertical direction rather than horizontally. This dimensional change allows integration density to increase without proportionally reducing the transistor footprint, thereby avoiding the processing difficulties associated with miniaturization while maintaining high integration capability.
Solution Approach 2:
The vertical channel is segmented into multiple portions (first channel portion along side surface, second channel portion on upper surface) with different gate insulating film thicknesses. This segmentation allows optimized electrical characteristics for each region, maintaining performance without requiring proportional size reduction that would increase processing difficulty.
2Area of stationary object
If transistor size is reduced to increase integration, then device area is improved, but transistor performance degrades
Solution Approach 1:
By extending the channel vertically rather than horizontally, the patent achieves high integration density without reducing the horizontal device footprint. This maintains adequate transistor dimensions for reliable operation while increasing the number of transistors that can be integrated in the vertical direction.
Solution Approach 2:
Different portions of the vertical channel have different gate insulating film thicknesses (thinner at sides, thicker at top), optimizing electrical characteristics for each region. This local optimization maintains high performance without requiring uniform size reduction that would degrade overall transistor reliability.
3Quantity of substance
If channel length is reduced to increase integration, then integration density is improved, but operating margin decreases
Solution Approach 1:
The channel is extended in the vertical dimension rather than being shortened horizontally, allowing high integration density while maintaining adequate effective channel length for sufficient operating margin and electrical stability.
Solution Approach 2:
The gate insulating film thickness is varied along the vertical channel (thinner at sides, thicker at top), creating parameter gradients that optimize electrical characteristics. This allows maintaining adequate channel dimensions for operating margin while achieving high integration through vertical structuring.
4Area of stationary object
If non-active area is reduced to increase integration, then device area is improved, but driving current capability is limited
Solution Approach 1:
The vertical channel structure allows the active area to extend vertically without increasing the horizontal device footprint. This enables high integration density while maintaining adequate active area for sufficient driving current capability, as the vertical extension does not consume additional non-active area.
Data Source
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AI summary
An electronic device can include a panel; a driver circuit configured to drive the panel; and a transistor disposed in the panel, the transistor including a first electrode disposed on a substrate, an insulation pattern disposed on the substrate, the insulation pattern overlapping with an edge of the first electrode, a second electrode disposed on an upper surface of the insulation pattern, an active layer disposed on the first electrode, the insulation pattern and the second electrode, a gate insulating film disposed on the active layer, and a gate electrode disposed on the gate insulating film, in which a first portion of the active layer overlaps with the first electrode, a second portion of the active layer overlaps with the second electrode, and a channel area of the active layer is between the first portion of the active layer and the second portion of the active layer, and the channel area includes a first channel portion disposed along a side surface of the insulation pattern, and a second channel portion disposed on a portion of the upper surface of the insulation pattern, the second channel portion extending from an edge of the second electrode to the first channel portion.