Vertical Transistor Phase Change Memory Cell with Constricted Features
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Solution Overview
Problem
Current methods face challenges in reliably and reproducibly forming constricted phase change material (PCM) features in densely packed memory cell arrays, which are necessary for reducing the magnitude of the switching current pulse required for PCM-based memory cells, as they often exceed the tolerance of modern integrated circuits.
Innovation Solution
The method involves forming constricted PCM features by creating a series of doped features and sacrificial layers in integrated circuits, allowing for the precise placement and confinement of phase change materials, enabling high localized current densities and reduced switching current pulses through vertical transistors and dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the switching current pulse magnitude is reduced by confining current to narrow PCM features, then the current magnitude becomes compatible with modern integrated circuits, but it becomes challenging to reliably and reproducibly form constricted PCM features with suitably narrow dimensions
Solution Approach 1:
The patent transitions from planar photolithography to vertical nanowire formation, moving the constriction problem into the third dimension. By forming nanowires with diameters of 10-50 nm through vertical growth rather than lateral patterning, the invention achieves dimensional precision that cannot be obtained through conventional photolithography, while maintaining reliability through self-aligned vertical transistor structures
Solution Approach 2:
The patent introduces sacrificial layers as intermediary structures that enable precise formation of constricted PCM features. These sacrificial layers serve as templates and masks during the formation process, allowing controlled deposition and etching steps to create narrow nanowire structures with high precision before being removed to leave the final constricted PCM features
2Ease of manufacture
If conventional photolithography is used to form PCM features, then the manufacturing process is simpler, but the achievable feature dimensions are larger than required for low switching current
Solution Approach 1:
The patent replaces conventional photolithography (optical/mechanical system) with atomic layer deposition and chemical vapor deposition processes. These deposition-based methods enable precise control of nanowire dimensions at the atomic level, achieving feature sizes of 10-50 nm that are an order of magnitude smaller than what conventional photolithography can reliably produce
Solution Approach 2:
The patent changes the fundamental parameters of the fabrication process by transitioning from top-down photolithographic patterning to bottom-up deposition-based nanowire growth. By controlling deposition temperature, pressure, and precursor flow rates, the invention achieves precise dimensional control of PCM features with widths of 10-50 nm, far below the diffraction limit of conventional photolithography
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the reliable and reproducible formation of PCM features with dimensions smaller than those achievable by conventional photolithography, reducing the switching current pulse magnitude to values compatible with modern integrated circuits, enhancing memory cell performance and capacity.
Implementation Method 1
The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal
Implementation Method 2
The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein
Implementation Method 3
The confinement of the switching current to this narrow feature results in high localized current density, and, in turn, in high localized ohmic heating
Data Source
AI summary
A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.