Vertical Transistor Pillar Fabrication for Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As transistors in semiconductor devices are miniaturized, they face issues like short channel effects and increased leakage current, which are not adequately addressed by conventional methods, and there is a need to improve electrical isolation and reduce coupling effects between adjacent transistors in vertical transistor arrays.
Innovation Solution
A method involving the formation of trenches around pillars, oxidation processes to create oxide layers for insulation, and the use of shielding layers between transistors to enhance electrical isolation and reduce coupling effects, including the formation of undercuts and conductive layers to improve transistor design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the dimension of the transistor is reduced to accelerate operating speed and meet miniaturization demands, then the operating speed and integration level are improved, but short channel effect and decrease in turn-on current occur
Solution Approach 1:
The patent transitions from a conventional horizontal transistor structure to a vertical transistor structure formed in a deep trench of the substrate. This dimensional change allows the channel to extend vertically rather than horizontally, enabling better control of the channel region and reduction of short channel effects while maintaining miniaturization benefits for accelerating operating speed and improving integration level.
2Reliability
If dopant concentration in the channel region is enhanced to resolve short channel effect, then the turn-on current is improved, but leakage current increases affecting device reliability
Solution Approach 1:
The patent applies different dopant concentrations to different regions: high dopant concentration is applied to the source and drain regions to ensure low resistance and high turn-on current, while the channel region maintains lower dopant concentration to minimize leakage current. This localized differentiation resolves the contradiction by optimizing each region's electrical properties independently.
3Ease of manufacture
If conventional horizontal transistor structure is used, then the manufacturing process is simple, but electrical isolation between adjacent transistors is poor and coupling effect is high
Solution Approach 1:
The patent employs a vertical transistor structure where the channel extends vertically in a deep trench, creating natural electrical isolation between adjacent transistors through the substrate depth. This vertical configuration inherently reduces coupling effects between neighboring devices while maintaining manufacturing feasibility through established trench formation and filling processes.
4Reliability
If vertical transistor structure is formed in deep trench or on silicon pillars, then electrical isolation and integration level are improved, but device complexity increases
Solution Approach 1:
The patent segments the transistor structure into distinct functional regions within the vertical trench: source region, channel region, and drain region, with insulation layers strategically positioned to provide electrical isolation. This segmentation approach enables improved electrical isolation between adjacent transistors while organizing the complex vertical structure into manageable, functionally-defined segments that can be fabricated using systematic process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively improves electrical isolation and reduces coupling effects between transistors, enhancing the performance and reliability of vertical transistor arrays by preventing short circuits and leakage currents.
Implementation Method 1
the insulation layer is formed by performing an oxidation process to oxidize sidewalls of each opening so as to form an oxide layer
Implementation Method 2
the filling layer is formed by chemical vapor deposition
Data Source
AI summary
Provided is a method for fabricating a semiconductor device, which includes the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar, and a doped region is disposed at a bottom of each pillar. An insulation layer is formed below each doped region. In addition, a gate and a gate dielectric are formed on the sidewalls of each pillar.