Vertical Transistor Pillar Stability and Bit Line Resistance
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Solution Overview
Problem
In semiconductor devices with vertical transistors, the neck pillar structure is prone to collapse due to weak supporting forces, and the high aspect ratio of active pillars complicates the formation of stable structures and increases bit line resistance, making it difficult to remove gate conductive layers and apply metal layers without causing bridges between pillars.
Innovation Solution
The solution involves forming neck-free active pillars with a reduced height, using spacers and epitaxial layers to stabilize the structure, and creating word lines with exposed sidewalls to connect vertical gates, while also forming second active pillars over the first active pillars to enhance stability and reduce bit line resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a neck pillar structure is used to support the active pillar, then the active pillar can be formed with higher integration density, but the neck pillar has weak supporting force and may collapse in subsequent processes
Solution Approach 1:
The invention removes the neck pillar structure entirely, forming a neck-free active pillar. This eliminates the weak supporting force problem while maintaining the integration density benefits through direct formation of the active pillar structure without the intermediate neck section.
Solution Approach 2:
The invention performs preliminary actions by forming the active pillar with optimized dimensions and structural characteristics before subsequent processing steps. The active pillar is prepared in advance with sufficient mechanical strength to withstand subsequent etching, deposition, and CMP processes without collapse.
2Manufacturing precision
If the active pillar height is increased to maintain channel length, then the aspect ratio increases making it difficult to form stable structures, but reducing height affects transistor performance
Solution Approach 1:
The invention changes the geometric parameters of the active pillar, specifically optimizing the height and width dimensions to achieve an appropriate aspect ratio. By adjusting these parameters, the pillar maintains sufficient mechanical stability while preserving the required channel length for transistor operation.
Solution Approach 2:
The invention applies different structural characteristics to different regions of the active pillar. The pillar has uniform cross-section without a neck, providing consistent mechanical properties throughout its height, which enhances overall stability while maintaining the required channel length.
3Ease of manufacture
If ion implantation is used to form the buried bit line, then the bit line can be formed between active pillars, but the resistance of the buried bit line becomes extremely high
Solution Approach 1:
The invention forms a composite structure by depositing a metal layer (such as tungsten or copper) over the ion-implanted buried bit line. This composite structure combines the benefits of ion implantation for forming the bit line between pillars with the low electrical resistance of metal, achieving both ease of manufacture and reliable electrical performance.
4Stability of the object's composition
If the gate conductive layer is deposited to cover the active pillar top, then complete coverage is achieved, but it becomes difficult to remove the gate conductive layer surrounding regions outside the channel region and the pad nitride layer is damaged
Solution Approach 1:
The invention applies partial action by depositing the gate conductive layer to a controlled thickness that provides sufficient coverage over the active pillar top while leaving excess material that can be selectively removed. The etch process selectively removes the gate conductive layer from regions outside the channel region without damaging the pad nitride layer, achieving both complete coverage and ease of removal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents pillar collapse, allows for easy removal of gate conductive layers, and reduces bit line and word line resistances, maintaining a stable pillar structure even with increasing aspect ratios and ensuring consistent channel lengths.
Implementation Method 1
a spacer layer is deposited over the word line
Implementation Method 2
a semiconductor layer is grown over the first active pillars to form a plurality of second active pillars
Data Source
AI summary
A semiconductor device with a vertical transistor includes a plurality of active pillars; a plurality of vertical gates surrounding sidewalls of the active pillars; a plurality of word lines having exposed sidewalls whose surfaces are higher than the active pillars and connecting the adjacent vertical gates together; and a plurality of spacers surrounding the exposed sidewalls of the word lines over the vertical gates.