Vertical Transistor Reentrant Profile Selective Deposition
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Solution Overview
Problem
Conventional photolithographic techniques struggle to pattern directly on vertical substrate walls, leading to inconsistent deposition thickness and high costs in semiconductor device manufacturing, particularly for large-scale electronics production.
Innovation Solution
A method involving a substrate with a gate material layer stack and a reentrant profile, where an electrically insulating material layer is deposited, followed by a patterned deposition inhibiting material, allowing for selective area deposition of semiconductor material layers, reducing reliance on high-resolution alignment and enabling cost-effective large-scale production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithographic techniques are used to pattern vertical substrate walls, then pattern alignment can be achieved, but deposition thickness becomes inconsistent and manufacturing cost increases
Solution Approach 1:
The patent applies preliminary action by depositing the semiconductor material layer conformally over the entire gate material layer stack before any patterning occurs. This ensures uniform thickness deposition across all surfaces including vertical walls, and subsequent patterning steps only remove excess material rather than attempting to control deposition thickness during the deposition process itself.
Solution Approach 2:
The patent extracts the patterning function from the deposition process. Instead of attempting to pattern during deposition (which causes thickness inconsistency), the method deposits material conformally first, then separately removes excess material through etching or mechanical means to achieve the final pattern. This separation resolves the contradiction between uniform deposition and pattern alignment.
2Ease of manufacture
If conventional photolithographic techniques with filler materials are used for vertical wall patterning, then direct patterning on vertical walls is achieved, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent uses preliminary action by providing the gate material layer stack with a reentrant profile before semiconductor material deposition. This pre-formed profile naturally guides the conformal deposition process to achieve proper pattern alignment without requiring additional filler materials or complex photolithographic alignment steps during deposition.
Solution Approach 2:
The patent inverts the conventional approach by not attempting to pattern the vertical walls directly during deposition. Instead, it deposits material conformally over the entire structure and then removes excess material. This inversion eliminates the need for complex filler material processes while maintaining precise pattern alignment.
3Manufacturing precision
If oxide deposition is performed only in upper regions of vertical walls using etching stop layers, then selective deposition is achieved, but process complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts the selective deposition control function from complex multi-layer etching stop layer structures. By using a reentrant profile combined with conformal deposition followed by excess material removal, the method achieves selective deposition control without requiring multiple etching stop layers, thereby reducing process complexity while maintaining precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise and uniform deposition on vertical surfaces, reducing manufacturing complexity and costs, while enabling the production of large-scale low-cost electronics systems with improved semiconductor component performance.
Implementation Method 1
depositing a semiconductor material layer using a conformal coating process such as atomic layer deposition
Implementation Method 2
The reentrant profile allows portions of the substrate to be shielded from material deposited using a directional deposition process
Data Source
AI summary
Producing a vertical transistor includes providing a substrate including a gate material layer stack with a reentrant profile. An electrically insulating material layer is deposited over a portion of the gate material layer stack and over a portion of the substrate. A patterned deposition inhibiting material is deposited over the electrically insulating material layer. A semiconductor material layer is deposited over the electrically insulating material layer using a selective area deposition process in which the semiconductor material layer is not deposited over the patterned deposition inhibiting material.