Vertical Transistor for Resistive Memory Area Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current resistive memory technologies occupy significant substrate surface area, limiting further miniaturization and efficiency in memory cell design.
Innovation Solution
The implementation of embedded vertical gates and doped regions in a semiconductor substrate, allowing for the formation of mini-wells and shared conduction regions, reduces substrate surface area by using vertical gates as both selection and isolation elements, and optimizing transistor channel formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional planar transistors with separate selection and isolation structures are used, then the memory cell can function properly, but the substrate surface area occupied by each memory cell is large
Solution Approach 1:
The patent merges the selection function and isolation function into a single embedded vertical gate structure. The gate is formed in a trench that extends through the substrate, and the same gate structure simultaneously provides both selection control and isolation from adjacent memory cells, eliminating the need for separate isolation trenches and reducing overall cell area.
Solution Approach 2:
The patent transitions from a planar two-dimensional transistor layout to a three-dimensional vertical structure. The gate is embedded vertically in the substrate along the direction perpendicular to the surface, allowing current to flow laterally through the channel region while the gate controls it from above and below. This vertical dimension enables higher integration density.
2Reliability
If isolating trenches are used to separate memory cells, then adjacent cells are electrically isolated, but the substrate surface area increases
Solution Approach 1:
The isolation function is merged into the gate trench structure itself. The trench that houses the embedded gate also serves as the isolation structure between adjacent memory cells. The trench is filled with dielectric material that provides electrical isolation, eliminating the need for additional separate isolation trenches.
Solution Approach 2:
The embedded gate structure performs multiple functions simultaneously: it provides selection control for the memory cell, acts as an isolation barrier from adjacent cells, and defines the active area for the variable impedance element. This multi-functionality reduces the total number of structures needed.
3Ease of manufacture
If separate selection and isolation structures are implemented, then the transistor can be properly controlled, but the manufacturing process becomes more complex
Solution Approach 1:
The patent combines the gate formation and isolation structure creation into a single trench etching and filling process. The same trench that is etched to form the gate structure also serves as the isolation structure, meaning only one etching step and one filling step are needed instead of separate processes for gate formation and isolation.
Solution Approach 2:
The substrate is segmented into isolated mini-wells by the trench structure, with each well containing a complete memory cell. This segmentation is achieved through a single continuous trench that runs through the substrate, simplifying the overall fabrication approach by creating natural boundaries for each cell.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the substrate surface area occupied by memory cells, enabling more efficient use of space and potentially improving memory cell performance by reducing the size of isolating trenches and shared conduction regions.
Implementation Method 1
a channel region extending along a first lateral face of the embedded gate, between a first deep doped region and a second doped region
Implementation Method 2
implanting, in the substrate, a second doped region forming a first conduction region of a select transistor
Data Source
AI summary
The present disclosure relates to a method of making a memory on semiconductor substrate, comprising: at least one data line, at least one selection line, at least one reference line, at least one memory cell comprising a select transistor having a control gate connected to the selection line, a first conduction terminal connected to a variable impedance element, the select transistor and the variable impedance element coupling the reference line to the data line, the select transistor comprising an embedded vertical gate produced in a trench formed in the substrate, and a channel region opposite a first face of the trench, between a first deep doped region and a second doped region on the surface of the substrate coupled to the variable impedance element.